ISPLSI2032A-80LT44I 데이터 시트보기 (PDF) - Lattice Semiconductor
부품명
상세내역
일치하는 목록
ISPLSI2032A-80LT44I Datasheet PDF : 15 Pages
| |||
Specifications ispLSI 2032/A
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
TEST 4
COND.
#2
DESCRIPTION1
-180
-150
-135
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
tpd1
A 1 Data Prop. Delay, 4PT Bypass, ORP Bypass – 5.0 – 5.5 – 7.5 ns
tpd2
fmax
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
A
A
–
–
–
A
–
–
–
2 Data Prop. Delay
–
3 Clk Frequency with Internal Feedback 3
180
4
Clk Frequency with Ext. Feedback
( ) 1
tsu2 + tco1
125
5 Clk Frequency, Max. Toggle
200
6 GLB Reg Setup Time before Clk, 4 PT Bypass 3.0
7 GLB Reg. Clk to Output Delay, ORP Bypass
–
8 GLB Reg. Hold Time after Clk, 4 PT Bypass 0.0
9 GLB Reg. Setup Time before Clk
4.0
10 GLB Reg. Clk to Output Delay
–
7.5
–
–
–
–
4.0
–
–
4.5
– 8.0 – 10.0 ns
154 – 137 – MHz
S 111 – 100 – MHz
N 167 – 167 – MHz
IG 3.0 – 4.0 – ns
– 4.5 – 4.5 ns
S 0.0 – 0.0 – ns
E 4.5 – 5.5 – ns
D– 5.0 – 5.5 ns
th2
tr1
trw1
tptoeen
– 11 GLB Reg. Hold Time after Clk
A 12 Ext. Reset Pin to Output Delay
– 13 Ext. Reset Pulse Duration
B 14 Input to Output Enable
0.0 – 0.0
W – 7.0 –
E4.0 – 4.5
N– 10.0 –
–
8.0
–
11.0
0.0
–
5.0
–
–
10.0
–
12.0
ns
ns
ns
ns
tptoedis
tgoeen
tgoedis
twh
C
B
C
–
15 Input to Output Disable
R 16 Global OE Output Enable
17 Global OE Output Disable
FO 18 Ext. Synchronous Clk Pulse Duration, High
– 10.0 – 11.0 – 12.0
– 5.0 – 5.0 – 6.0
– 5.0 – 5.0 – 6.0
2.5 – 3.0 – 3.0 –
ns
ns
ns
ns
twl
– 19 Ext. Synchronous Clk Pulse Duration, Low
2.5 – 3.0
E 1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2 2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
ispLSI 203 4. Reference Switching Test Conditions section.
–
3.0 – ns
Table 2-0030B-180/2032
USE
5
Share Link: 