ISPLSI2032A-80LT44I 데이터 시트보기 (PDF) - Lattice Semiconductor
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ISPLSI2032A-80LT44I Datasheet PDF : 15 Pages
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Specifications ispLSI 2032/A
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER #2
DESCRIPTION
-110
-80
UNITS
MIN. MAX. MIN. MAX.
Inputs
tio
tdin
GRP
tgrp
GLB
t4ptbpc
t4ptbpr
t1ptxor
t20ptxor
20 Input Buffer Delay
21 Dedicated Input Delay
22 GRP Delay
23 4 Product Term Bypass Path Delay (Combinatorial)
24 4 Product Term Bypass Path Delay (Registered)
25 1 Product Term/XOR Path Delay
26 20 Product Term/XOR Path Delay
– 1.7 – 2.2 ns
– 3.4 – 4.8 ns
NS – 1.7 – 2.6 ns
IG – 4.9 – 7.2 ns
S – 4.8 – 7.2 ns
DE – 6.2 – 8.8 ns
– 6.8 – 9.2 ns
txoradj
tgbp
tgsu
tgh
27 XOR Adjacent Path Delay 3
28 GLB Register Bypass Delay
29 GLB Register Setup Time befor Clock
30 GLB Register Hold Time after Clock
–
W–
E 0.5
N 4.0
7.5
0.1
–
–
– 10.2
– 0.0
0.1 –
6.0 –
ns
ns
ns
ns
tgco
tgro
tptre
tptoe
31 GLB Register Clock to Output Delay
R 32 GLB Register Reset to Output Delay
33 GLB Product Term Reset to Register Delay
FO 34 GLB Product Term Output Enable to I/O Cell Delay
– 0.6
– 1.8
– 5.9
– 7.1
– 0.4 ns
– 2.2 ns
– 8.8 ns
– 12.8 ns
tptck
ORP
torp
torpbp
Outputs
tob
tsl
toen
todis
tgoe
Clocks
35 GLB Product Term Clock Delay
2E 36 ORP Delay
3 37 ORP Bypass Delay
20 38 Output Buffer Delay
I 39 Output Slew Limited Delay Adder
S 40 I/O Cell OE to Output Enabled
L 41 I/O Cell OE to Output Disabled
isp 42 Global Output Enable
4.0 7.0 5.5 9.5 ns
– 1.5 – 2.1 ns
– 0.5 – 0.6 ns
– 1.2 – 2.4 ns
– 10.0 – 10.0 ns
– 4.0 – 6.4 ns
– 4.0 – 6.4 ns
– 3.0 – 5.6 ns
tgy0
E tgy1/2
S Global Reset
U tgr
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
45 Global Reset to GLB
3.2 3.2 4.6 4.6 ns
3.2 3.2 4.6 4.6 ns
– 9.0 – 12.8 ns
1. Internal Timing Parameters are not tested and are for reference only.
Table 2-0036C-110/2032
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
8
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