GF9105A 데이터 시트보기 (PDF) - Unspecified
부품명
상세내역
일치하는 목록
GF9105A Datasheet PDF : 37 Pages
| |||
CLP_D1 AND CLP_D0 CONTROL BIT OPERATION
RND8/10 CLP_D1 CLP_D0
DESCRIPTION
0
0
0
Y/G, CB/B, CR/R Channels: Clipped to a 13-bit two’s complement number (Values -4096 to 4095)
KEY Channel: Clipped to an 11-bit two’s complement number (Values -1024 to +1023)
0
0
1
Y/G, CB/B, CR/R Channels: Clipped to a 12-bit two’s complement number (Values -2048 to 2047)
KEY Channel: Clipped to an 11-bit two’s complement number (Values -1024 to +1023)
0
1
0
Y/G, CB/B, CR/R, KEY Channels: Clipped to a 10-bit unsigned number (Values 0 to +1023)
0
1
1
Y/G, CB/B, CR/R, KEY Channels: Clipped to a 10-bit unsigned number (Values +4 to +1019)
1
0
0
Y/G, CB/B, CR/R Channels: Clipped to a 11-bit two’s complement number (Values -1024 to 1023)
KEY Channel: Clipped to an 9-bit two’s complement number (Values -256 to +255)
1
0
1
Y/G, CB/B, CR/R Channels: Clipped to a 10-bit two’s complement number (Values -512 to +511)
KEY Channel: Clipped to an 9-bit two’s complement number (Values -256 to +255)
1
1
0
Y/G, CB/B, CR/R, KEY Channels: Clipped to a 8-bit unsigned number (Values 0 to +255)
1
1
1
Y/G, CB/B, CR/R, KEY Channels: Clipped to a 8-bit unsigned number (Values +1 to +254)
formats as outlined in SMPTE 125M. (See TRS Insertion Section).
When OUTPUT/INPUT is set high, Processing Core output port C5 corresponds to device data port P1 and Processing Core
output port C8 corresponds to device data port P4. While OUTPUT/INPUT is set low, Processing Core output port C5
corresponds to device data port P5 and Processing Core output port C8 corresponds to device data port P8.
Single Link (SL/DL_OUT = 1)
When generating single link output data, the 4:4:4:4 data stream (SMPTE RP174 compliant) exits the GF9105A Processing
Core from Processing Core output C5. While OUTPUT/INPUT = 0 Processing Core port C5 corresponds to device data port
P5(refer to Figure 4a). While OUTPUT/INPUT = 1 Processing Core Port C5 corresponds to device data port P1 (refer to
Figure 4b). In this mode, the input clock (CLK) is operating at 54 MHz. Also, note that the MUXED_OUT control bit must be
set LOW (MUXED_OUT = 0) and the 4:4:4:4/4:2:2:4_OUT control bit must be set HIGH (4:4:4:4/4:2:2:4_OUT = 1)
.
MUXED_OUT, 4:4:4:4/4:2:2:4_OUT AND SL/DL_OUT CONTROL BITS
MUXED_OUT
4:4:4:4/4:2:2:4_OUT
SL/DL_OUT
DESCRIPTION
0
0
0
Output data in a 4:2:2:4 dual link multiplexed format.
0
1
0
Output data in a 4:4:4:4 dual link multiplexed format.
0
1
1
Output data in a 4:4:4:4 single link multiplexed format.
1
0
XX
Output 4:2:2:4 data in a non-multiplexed format.
1
1
XX
Output 4:4:4:4 data in a non-multiplexed format.
When the device is configured for outputting non-multiplexed data and RND8/10 is set low, 13-bit two’s complement,12-bit
two’s complement, or 10-bit unsigned data may be output on Processing Core output data ports C5-C7 and 11-bit two’s
complement or 10-bit unsigned data output on the Processing Core output data port C8. The output data will be embedded
within the physical 13-bit output ports as shown in the following tables. Note that when HVF_OUT=1 and OUTPUT/INPUT=1
b12 of the GF9105As 13-bit two’s complement output is not available. In this case, the 13-bit output data is clipped to a 12-bit
two’s complement number. Bit 12 (b12) of the 13 bit physical interface is used to output the H, V and F output signals. In this
case, 13 bit output data is clipped 13 bit to a 12 bit two’s complement number.
521 - 88 - 03
16
Share Link: 