GF9105A 데이터 시트보기 (PDF) - Unspecified

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GF9105A

Component Digital Transcoder

Unspecified 

Single Link (SL/DL_IN = 1)

When operating with single link input data, the 4:4:4:4 data stream (SMPTE RP174 compliant) enters the GF9105A

Processing Core from Processing Core input C1.

While OUTPUT/INPUT = 0 Processing Core Port C1 corresponds to device data port P1 (refer to Figures 4a and 4c). While

OUTPUT/INPUT = 1 Processing Core Port C1 corresponds to device data port P5 (refer to Figures 4b and 4d). In this

mode, the input clock (CLK) is operating at 54 MHz. Also, note that the MUXED_IN control bit must be set low (MUXED_IN

= 0).

MUXED_IN AND SL/DL_IN CONTROL BITS

MUXED_IN

SL/DL_IN

DESCRIPTION

0

0

Input is in a dual link multiplexed format.

0

1

Input is in a single link multiplexed format.

1

XX

Input is in a non-multiplexed format.

SYNCHRONIZATION

In order to properly synchronize the input de-multiplexer, the GF9105A requires a SYNC_CB control signal input. For

multiplexed input data, SYNC_CB should change from high to low at the start of an even numbered CB sample. After

synchronizing the device with the incoming data stream, SYNC_CB can remain low until re-synchronization is desired. Refer

to Figure 7a for timing of SYNC_CB with a dual link multiplexed input data stream. Refer to Figure 7b for timing of SYNC_CB

with a single link multiplexed input data signal. The timing shown may be referred to as “standard SYNC_CB timing”.

In order to simplify overall system design, the HSYNC output from the GS9001 EDH Coprocessor may be used as a

SYNC_CB signal when operated with a 4:2:2 or dual link 4:4:4:4 input signal. In this mode of operation, the 10 bit multiplexed

data entering the GF9105A must be fed from the output of the GS9001 and the GF9105A’s SYNC_CB input must be fed from

the GS9001’s HSYNC output (Refer to Figure 8a). To use this mode of operation the GF9105A’s GS9001 control bit (Refer to

Host Programming Section) must be set high. When operated with a 4:2:2 or a dual link 4:4:4:4 input signal and when the

GS9001 control bit is set high, the GS9001’s HSYNC, VSYNC, and FIELD output signals may also be used to drive the

GS9105A’s output multiplexer. Refer to the Timing Reference Signal section for information regarding this.

When dealing with single link 4:4:4:4 input or output signals “standard” SYNC_CB timing above must be used. When using

standard SYNC_CB and HVF timing, the GS9001 control must be set low. The GS9020 may be used to provide such

standard SYNC_CB timing and HVF. When operated in this manner, the 10 bit multiplexed data entering the GF9105A must

be fed from the output of the GS9020 and the GF9105A’s SYNC_CB and HVF inputs must be fed from the GS9020’s H, V, F

outputs. The same GS9020/GF9105A configuration may also be used when interfacing the GF9105A to a standard 4:2:2 or

dual link 4:4:4:4 link input signal. In this case, the GS9001 control bit must still be set low.

GS9001 CONTROL BIT

GS9001

DESCRIPTION

0

Standard SYNC_CB and H,V,F timing. Simple interface to GS9020.

1

Modified SYNC_CB and H, V, F timing. Simple interface to GS9001.

NOTE: Standard SYNC_CB and H, V, F timing must be used when receiving or generating single link 4:4:4:4 signals.

With non-multiplexed input data, SYNC_CB must change from high to low at the start of an even-numbered CB sample. It is

important to note that SYNC_CB changes from high to low on an even-numbered CB sample and not an odd-numbered

sample. After synchronizing the device with the incoming data stream, the SYNC_CB signal can remain low until re-

synchronization is desired. Refer to Figure 7c for timing of SYNC_CB with non-multiplexed input data. Following the input de-

multiplexer, data is passed to the Horizontal Blanking section of the device.

HORIZONTAL BLANKING

When H_BLANK is high, all four channels of input are forced to a user selectable set of levels. When H_BLANK is low data is

passed through the Horizontal Blanking section of the device unmodified. Refer to Figures 10a and 10b for typical timing of

H_BLANK with multiplexed input data and Figure 10c for typical timing with non-multiplexed input data. In these figures, a

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