AS7C33256PFS32A 데이터 시트보기 (PDF) - Alliance Semiconductor

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AS7C33256PFS32A

3.3V 256K × 32/36 pipelined burst synchronous SRAM

Alliance Semiconductor 

AS7C33256PFS32A

AS7C33256PFS36A

®

AC test conditions

• Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure C.

• Input pulse level: GND to 3V. See Figure A.

• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.

• Input and output timing reference levels: 1.5V.

+3.0V

90%

10%

GND

90%

10%

Figure A: Input waveform

DOUT

Z0 = 50Ω

50Ω

VL = 1.5V

for 3.3V I/O;

30 pF* = VDDQ/2

for 2.5V I/O

Figure B: Output load (A)

Thevenin equivalent:

DOUT

353Ω / 1538Ω

+3.3V for 3.3V I/O;

/+2.5V for 2.5V I/O

319Ω / 1667Ω

5 pF*

GND *including scope

and jig capacitance

Figure C: Output load (B)

Notes

1 For test conditions, see AC Test Conditions, Figures A, B, and C.

2 This parameter measured with output load condition in Figure C.

3 This parameter is sampled, but not 100% tested.

4 tHZOE is less than tLZOE, and tHZC is less than tLZC at any given temperature and voltage.

5 tCH measured as high above VIH, and tCL measured as low below VIL.

6 This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must

meet the setup and hold times for all rising edges of CLK when chip is enabled.

7 Write refers to GWE, BWE, and BW[a:d].

8 Chip select refers to CE0, CE1, and CE2.

11/30/04, v.3.1

Alliance Semiconductor

P. 17 of 20

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