AS7C33256PFS32A 데이터 시트보기 (PDF) - Alliance Semiconductor

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AS7C33256PFS32A

3.3V 256K × 32/36 pipelined burst synchronous SRAM

Alliance Semiconductor 

®

Timing waveform of read/write cycle (ADSP Controlled; ADSC High)

CLK

tCYC

tCH

tCL

ADSP

tADSPS

tADSPH

Address

tAS

tAH

A1

A2

A3

GWE

tWS

tWH

CE0, CE2

AS7C33256PFS32A

AS7C33256PFS36A

CE1

ADV

OE

Din

Dout

tADVS

tADVH

tCD

tLZC

Q(A1)

tDS tDH

D(A2)

tHZOE

tLZOE

tOE

Q(A3)

tOH

Q(A3Ý01) Q(A3Ý10) Q(A3Ý11)

DSEL

Read

Q(A1)

Suspend

Read

Q(A1)

Read

Q(A2)

Suspend

Write

D(A 2)

Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.

Read

Q(A3)

ADV

Burst

Read

Q(A 3Ý01)

ADV

Burst

Read

Q(A 3Ý10)

ADV

Burst

Read

Q(A 3Ý11)

11/30/04, v.3.1

Alliance Semiconductor

P. 14 of 20

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