AS7C33256PFS32A 데이터 시트보기 (PDF) - Alliance Semiconductor
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AS7C33256PFS32A Datasheet PDF : 20 Pages
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AS7C33256PFS32A
AS7C33256PFS36A
®
Timing characteristics for 2.5 V I/O operation
–166
–133
Parameter
Symbol Min Max Min Max Unit
Clock frequency
Cycle time
Clock access time
Output enable low to data valid
Clock high to output low Z
Data output invalid from clock high
Output enable low to output low Z
Output enable high to output high Z
Clock high to output high Z
Output enable high to invalid output
Clock high pulse width
Clock low pulse width
Address setup to clock high
Data setup to clock high
Write setup to clock high
Chip select setup to clock high
Address hold from clock high
Data hold from clock high
Write hold from clock high
Chip select hold from clock high
ADV setup to clock high
ADSP setup to clock high
ADSC setup to clock high
ADV hold from clock high
ADSP hold from clock high
ADSC hold from clock high
1 See “Notes” on page 17
Snooze Mode Electrical Characteristics
fMax
– 166 – 133 MHz
tCYC
6
– 7.5 –
ns
tCD
- 3.8 - 4.2 ns
tOE
– 3.5 – 4.0 ns
tLZC
0
–
0
–
ns
tOH
1.5 – 1.5 –
ns
tLZOE
0
–
0
–
ns
tHZOE
– 3.5 – 4.0 ns
tHZC
– 3.5 – 4.0 ns
tOHOE
0
–
0
–
ns
tCH
2.4 – 2.5 –
ns
tCL
2.3 – 2.5 –
ns
tAS
1.7 – 1.7 –
ns
tDS
1.7 – 1.7 –
ns
tWS
1.7 – 1.7 –
ns
tCSS
1.7 – 1.7 –
ns
tAH
0.7 – 0.7 –
ns
tDH
0.7 – 0.7 –
ns
tWH
0.7 – 0.7 –
ns
tCSH
0.7 – 0.7 –
ns
tADVS
1.7
–
1.7
–
ns
tADSPS 1.7
–
1.7
–
ns
tADSCS 1.7
–
1.7
–
ns
tADVH 0.7
–
0.7
–
ns
tADSPH 0.7
–
0.7
–
ns
tADSCH 0.7
–
0.7
–
ns
Description
Current during Snooze Mode
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
Conditions
ZZ > VIH
Symbol
Min
Max
ISB2
30
tPDS
2
tPUS
2
tZZI
2
tRZZI
0
Notes1
2,3,4
2
2,3,4
2,3,4
2,3,4
5
5
6
6
6,7
6,8
6
6
6,7
6,8
6
6
6
6
6
6
Units
mA
cycle
cycle
cycle
11/30/04, v.3.1
Alliance Semiconductor
P. 11 of 20
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