AS7C33256PFS32A 데이터 시트보기 (PDF) - Alliance Semiconductor

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AS7C33256PFS32A

3.3V 256K × 32/36 pipelined burst synchronous SRAM

Alliance Semiconductor 

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Timing waveform of read/write cycle(ADSC controlled, ADSP = HIGH)

CLK

tADSCS

ADSC

tADSCH

tCYC

tCH

tCL

AS7C33256PFS32A

AS7C33256PFS36A

ADDRESS

A1

A2 A3 A4

GWE

tCSS tCSH

CE0,CE2

tAS

tAH

A5 A6 A7 A8 A9

tWS tWH

CE1

ADV

OE

Dout

Din

tOE

tLZOE

Q(A1)

Q(A2)

tHZOE

Q(A3)

Q(A4)

tLZOE

tOH

Q(A8)

Q(A9)

READ READ READ READ

Q(A1) Q(A2) Q(A3) Q(A4)

tDS

tDH

D(A5) D(A6)

D(A7)

WRITE WRITE WRITE READ READ

D(A5) D(A6) D(A7) Q(A8) Q(A9)

11/30/04, v.3.1

Alliance Semiconductor

P. 15 of 20

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