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전자부품 반도체 검색엔진( 무료 PDF 다운로드 ) - 데이터시트뱅크

ADSP-21366BBCZ-1AA 데이터 시트보기 (PDF) - Analog Devices

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ADSP-21366BBCZ-1AA
ADI
Analog Devices ADI
ADSP-21366BBCZ-1AA Datasheet PDF : 56 Pages
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Clock Input
Table 11. Clock Input
Parameter
200 MHz1
Min
Max
Timing Requirements
tCK
CLKIN Period
tCKL
CLKIN Width Low
tCKH
CLKIN Width High
tCKRF
tCCLK4
tVCO5
tCKJ6,7
CLKIN Rise/Fall (0.4 V to 2.0 V)
CCLK Period
VCO Frequency
CLKIN Jitter Tolerance
303
12.51
12.51
5.01
200
–250
100
3
10
600
+250
1 Applies to all 200 MHz models. See Ordering Guide on Page 54.
2 Applies to all 333 MHz models. See Ordering Guide on Page 54.
3 Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in the PMCTL register.
4 Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK.
5 See Figure 5 on Page 16 for VCO diagram.
6 Actual input jitter should be combined with AC specifications for accurate timing analysis.
7 Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.
Min
181
7.51
7.51
3.01
200
–250
333 MHz2
Max
100
3
10
800
+250
Unit
ns
ns
ns
ns
ns
MHz
ps
CLKIN
tCKH
tCK
tCKL
tCKJ
Figure 7. Clock Input
Clock Signals
The processor can use an external clock or a crystal. Refer to the
CLKIN pin description in Table 6 on Page 11. The user applica-
tion program can configure the processor to use its internal
clock generator by connecting the necessary components to the
CLKIN and XTAL pins. Figure 8 shows the component connec-
tions used for a fundamental frequency crystal operating in
parallel mode.
Note that the clock rate is achieved using a 16.67 MHz crystal
and a PLL multiplier ratio 16:1. (CCLK:CLKIN achieves a clock
speed of 266.72 MHz.) To achieve the full core clock rate, pro-
grams need to configure the multiplier bits in the
PMCTL register.
CLKIN
C1
22pF
ADSP-2136x
R1
1M Ω *
Y1
24.576MHz
XTAL
R2
47Ω *
C2
22pF
R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL
DRIVE POWER. REFER TO CRYSTAL
MANUFACTURER’S SPECIFICATIONS.
*TYPICAL VALUES
Figure 8. Recommended Circuit for Fundamental Mode Crystal Operation
Rev. G | Page 18 of 56 | March 2011

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