ADSP-21366BBCZ-1AA 데이터 시트보기 (PDF) - Analog Devices

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ADSP-21366BBCZ-1AA

SHARC Processors

Analog Devices 

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

• The product of CLKIN and PLLM must never exceed fVCO

(max) in Table 11 if the input divider is enabled

(INDIV = 1).

The VCO frequency is calculated as follows:

fVCO = 2 × PLLM × fINPUT

fCCLK = (2 × PLLM × fINPUT) ÷ (2 × PLLN)

where:

fVCO = VCO output

PLLM = Multiplier value programmed in the PMCTL register.

During reset, the PLLM value is derived from the ratio selected

using the CLK_CFG pins in hardware.

PLLN = 1, 2, 4, 8 based on the PLLD value programmed on the

PMCTL register. During reset this value is 1.

fINPUT = Input frequency to the PLL.

fINPUT = CLKIN when the input divider is disabled or

fINPUT = CLKIN ÷ 2 when the input divider is enabled

Note the definitions of the clock periods that are a function of

CLKIN and the appropriate ratio control shown in Table 9. All

of the timing specifications for the ADSP-2136x peripherals are

defined in relation to tPCLK. Refer to the peripheral specific sec-

tion for each peripheral’s timing information.

Table 9. Clock Periods

Timing

Requirements

tCK

tCCLK

tPCLK

Description

CLKIN Clock Period

Processor Core Clock Period

Peripheral Clock Period = 2 × tCCLK

Figure 5 shows core to CLKIN relationships with external oscil-

lator or crystal. The shaded divider/multiplier blocks denote

where clock ratios can be set through hardware or software

using the power management control register (PMCTL). For

more information, refer to the ADSP-2136x SHARC Processor

Hardware Reference.

CLKIN

XTAL

BUF

CLKIN

DIVIDER

f

INPUT

PMCTL

(INDIV)

PLL

LOOP

FILTER

fVCO

PLL

VCO

DIVIDER

fCCLK

CLK_CFGx/

PMCTL (2 × PLLM)

PMCTL

(PLLD)

PMCTL

(PLLBP)

DIVIDE

BY 2

CCLK

PCLK

RESET

fVCO ÷ (2 × PLLM)

PMCTL (CLKOUTEN)

DELAY OF

4096 CLKIN

CYCLES

RESETOUT

CLKOUT (TEST ONLY)*

*CLKOUT (TEST ONLY) FREQUENCY IS THE SAME AS f

INPUT.

THIS SIGNAL IS NOT SPECIFIED OR SUPPORTED FOR ANY DESIGN.

Figure 5. Core Clock and System Clock Relationship to CLKIN

RESETOUT

BUF

CORERST

Rev. G | Page 16 of 56 | March 2011

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