ADSP-21366BBCZ-1AA 데이터 시트보기 (PDF) - Analog Devices

부품명

상세내역

일치하는 목록

ADSP-21366BBCZ-1AA

SHARC Processors

Analog Devices 

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

PACKAGE INFORMATION

The information presented in Figure 4 provides details about

the package branding for the ADSP-2136x processor. For a

complete listing of product availability, see Ordering Guide on

Page 54.

a

ADSP-2136x

tppZ-cc

vvvvvv.x n.n

#yyww country_of_origin

S

Figure 4. Typical Package Brand

Table 7. Package Brand Information

Brand Key

t

pp

Z

cc

vvvvvv.x

n.n

#

yyww

Field Description

Temperature Range

Package Type

RoHS Compliant Designation

See Ordering Guide

Assembly Lot Code

Silicon Revision

RoHS Compliant Designation

Date Code

ESD CAUTION

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge

without detection. Although this product features

patented or proprietary protection circuitry, damage

may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to

avoid performance degradation or loss of functionality.

MAXIMUM POWER DISSIPATION

See Estimating Power for the ADSP-21362 SHARC Processors

(EE-277) for detailed thermal and power information regarding

maximum power dissipation. For information on package ther-

mal specifications, see Thermal Characteristics on Page 45.

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in Table 8 may cause perma-

nent damage to the device. These are stress ratings only;

functional operation of the device at these or any other condi-

tions greater than those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device

reliability.

Table 8. Absolute Maximum Ratings

Parameter

Internal (Core) Supply Voltage (VDDINT)

Analog (PLL) Supply Voltage (AVDD)

External (I/O) Supply Voltage (VDDEXT)

Input Voltage

Output Voltage Swing

Load Capacitance

Storage Temperature Range

Junction Temperature While Biased

Rating

–0.3 V to +1.5 V

–0.3 V to +1.5 V

–0.3 V to +4.6 V

–0.5 V to +3.8 V

–0.5 V to VDDEXT + 0.5 V

200 pF

–65°C to +150°C

125°C

TIMING SPECIFICATIONS

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results

for an individual device, the values given in this data sheet

reflect statistical variations and worst cases. Consequently, it is

not meaningful to add parameters to derive longer times. For

voltage reference levels, see Figure 39 on Page 44 under Test

Conditions .

Switching Characteristics specify how the processor changes its

signals. Circuitry external to the processor must be designed for

compatibility with these signal characteristics. Switching char-

acteristics describe what the processor will do in a given

circumstance. Use switching characteristics to ensure that any

timing requirement of a device connected to the processor (such

as memory) is satisfied.

Timing Requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices.

Core Clock Requirements

The processor’s internal clock (a multiple of CLKIN) provides

the clock signal for timing internal memory, processor core, and

serial ports. During reset, program the ratio between the proces-

sor’s internal clock frequency and external (CLKIN) clock

frequency with the CLK_CFG1–0 pins.

The processor’s internal clock switches at higher frequencies

than the system input clock (CLKIN). To generate the internal

clock, the processor uses an internal phase-locked loop (PLL,

see Figure 5). This PLL-based clocking minimizes the skew

between the system clock (CLKIN) signal and the processor’s

internal clock.

Voltage Controlled Oscillator

In application designs, the PLL multiplier value should be

selected in such a way that the VCO frequency never exceeds

fVCO specified in Table 11.

• The product of CLKIN and PLLM must never exceed 1/2

fVCO (max) in Table 11 if the input divider is not enabled

(INDIV = 0).

Rev. G | Page 15 of 56 | March 2011

Share Link: