AD5764(RevPrC) 데이터 시트보기 (PDF) - Analog Devices

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AD5764
(Rev.:RevPrC)

Complete, Quad, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC

Analog Devices 

AD5764

VREFIN

16-BIT

DAC

OUTPUT

I/V AMPLIFIER

VOUT

LDAC

DAC

REGISTER

INPUT

REGISTER

SCLK

SYNC

SDIN

INTERFACE

LOGIC

SDO

Figure 9. Simplified Serial Interface showing input loading

circuitry for one DAC Channel

TRANSFER FUNCTION

Table ? Shows the ideal input code to output voltage relationship

for the AD5764 for both straight binary and twos complement

data coding.

Preliminary Technical Data

The output voltage expression is given by

VOUT

=

−2 ×VREFIN

+

4

×

VREFIN

⎡

⎢⎣

D

65536

⎤

⎥⎦

where:

D is the decimal equivalent of the code loaded to the DAC.

VREFIN is the reference voltage applied at the REFIN pin.

ASYNCHRONOUS CLEAR (CLR)

CLR is an active low, level sensitive clear that allows the outputs

to be cleared to either 0 V (straight binary coding) or negative

full scale (twos complement coding). It is necessary to maintain

CLR low for a minimum amount of time (refer to Figure 3) for

the operation to complete. When the CLR signal is returned

high, the output remains at the cleared value until a new value is

programmed. The CLR signal has priority over LDAC and

SYNC. A clear can also be initiated through software by writing

the command 0x04XXXX to the AD5764.

Digital Input

Analog Output

Straight Binary Data Coding

MSB

LSB

1111

1000

1111

0000

1111

0000

1111

0001

1000

0000

0000

0000

0111

1111

1111

1111

0000

0000

0000

0000

Twos Complement Data Coding

MSB

LSB

0111

1111

1111

1111

0000

0000

0000

0001

0000

0000

0000

0000

1111

1000

1111

0000

1111

0000

1111

0000

VOUT

+2 VREF x (32767/32768)

+2 VREF x (1/32768)

0V

-2 VREF x (1/32768)

-2 VREF x (32767/32768)

VOUT

+2 VREF x (32767/32768)

+2 VREF x (1/32768)

0V

-2 VREF x (1/32768)

-2 VREF x (32767/32768)

Rev. PrC 21-Oct-04| Page 18 of 28

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