MAX9316A 데이터 시트보기 (PDF) - Maxim Integrated
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MAX9316A Datasheet PDF : 11 Pages
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1:5 Differential (LV)PECL/(LV)ECL/
HSTL Clock and Data Driver
grounded), allowing high-performance clock or data
distribution in systems with a nominal 5.0V supply. For
interfacing to differential (LV)ECL, the VEE range is
-3.0V to -5.5V (with VCC grounded). Output levels are
referenced to VCC and are considered (LV)PECL or
(LV)ECL, depending on the level of the VCC supply.
With VCC connected to a positive supply and VEE con-
nected to ground, the outputs are (LV)PECL. The out-
puts are (LV)ECL when VCC is connected to ground
and VEE is connected to a negative supply.
Input Bias Resistors
When the CLK and CLK inputs are open, the internal
bias resistors set the inputs to differential low state. The
inverting input (CLK) is biased with a 45kΩ pullup to
VCC and a 45kΩ pulldown to VEE. The noninverting
input (CLK) and SCLK are biased with a 45kΩ pullup to
VCC and a 30kΩ pulldown to VEE. The single-ended
inputs (SEL, EN) are each biased with a 30kΩ pulldown
to VEE and a 30kΩ pullup to VCC.
Differential Clock Input Limits
The maximum magnitude of the differential signal applied
to the differential clock input is 3.0V. This limit also
applies to the difference between any reference voltage
input and a single-ended input. Specifications for the high
and low voltages of a differential input (VIHD and VILD)
and the differential input voltage (VIHD - VILD) apply
simultaneously.
Single-Ended Clock Input and VBB
The differential clock input can be configured to accept
a single-ended input. This is accomplished by connect-
ing the on-chip reference voltage, VBB, to the inverting
or noninverting input of the differential input as a refer-
ence. For example, the differential CLK, CLK input is
converted to a noninverting, single-ended input by con-
necting VBB to CLK and connecting the single-ended
input signal to CLK. Similarly, an inverting configuration
is obtained by connecting VBB to CLK and connecting
the single-ended input to CLK. With a differential input
configured as single ended (using VBB), the single-
ended input can be driven to VCC and VEE or with a
single-ended (LV)PECL/(LV)ECL signal. Note that the
single-ended input must be least VBB ±95mV or a dif-
ferential input of at least 95mV to switch the outputs to
the VOH and VOL levels specified in the DC Electrical
Characteristics table.
When using the VBB reference output, bypass it with a
0.01µF ceramic capacitor to VCC. If the VBB reference
is not used, leave it open. The VBB reference can
source or sink 0.5mA. Use VBB only for an input that is
on the same device as the VBB reference.
Applications Information
Supply Bypassing
Bypass VCC to VEE with high-frequency, surface-mount,
ceramic, 0.1µF and 0.01µF capacitors in parallel as
close to the device as possible, with the 0.01µF capaci-
tor closest to the device. Use multiple parallel vias to
minimize parasitic inductance. When using the VBB ref-
erence output, bypass it with a 0.01µF ceramic capaci-
tor to VCC (if the VBB reference is not used, it can be
left open).
Controlled-Impedance Traces
Input and output trace characteristics affect the perfor-
mance of the MAX9316A. Connect input and output
signals with 50Ω characteristic impedance traces.
Minimize the number of vias to prevent impedance dis-
continuities. Reduce reflections by maintaining the 50Ω
characteristic impedance through cables and connec-
tors. Reduce skew within a differential pair by matching
the electrical length of the traces.
Output Termination
Terminate outputs with 50Ω to VCC - 2V or use an
equivalent Thevenin termination. When a single-ended
signal is taken from a differential output, terminate both
outputs. For example, if Q0 is used as a single-ended
output, terminate both Q0 and Q0.
Chip Information
TRANSISTOR COUNT: 616
PROCESS: Bipolar
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