MAX9316A 데이터 시트보기 (PDF) - Maxim Integrated

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MAX9316A

1:5 Differential (LV)PECL/(LV)ECL/HSTL Clock and Data Driver

Maxim Integrated 

1:5 Differential (LV)PECL/(LV)ECL/

HSTL Clock and Data Driver

AC ELECTRICAL CHARACTERISTICS

(VCC - VEE = 3.0V to 5.5V, outputs are loaded with 50Ω ±1% to VCC - 2V, input frequency ≤ 1.5GHz, input transition time = 125ps

(20% to 80%), SEL = high or low, EN = low, VIHD = VEE + 1.2V to VCC, VILD = VEE to VCC - 0.15V, VIHD - VILD = 0.15V to 3V, unless

otherwise noted. Typical values are at VCC - VEE = 5.0V.) (Notes 1, 6)

PARAMETER

CLK to Q_ Delay

(Differential)

SYMBOL CONDITIONS

tPLHD1,

tPHLD1

Figure 2

-40°C

+25°C

+85°C

UNITS

MIN TYP MAX MIN TYP MAX MIN TYP MAX

290

400 310

440 300

520 ps

SCLK to Q_ Delay

tPLHD3,

tPHLD3

VIL = VCC - 1.55V,

VIH = VCC - 1.09V,

Figure 3

290

400 310

440 300

520 ps

Output-to-Output

Skew (Note 7)

tSKOO

5 30

20 40

20 50 ps

Part-to-Part Skew

(Note 8)

tSKPP

110

130

220 ps

Added Random

Jitter (Note 9)

tRJ

fIN = 1.5GHz clock

0.8 1.2

0.8 1.2

0.8 1.2 ps (RMS)

Added

Deterministic Jitter

(Note 9)

1.5Gbps 2E23 - 1

tDJ

PRBS pattern

50 70

50 70

50 70 PsP-P

Switching

Frequency

(VOH - VOL)

fMAX ≥ 400mV,

1.5

Figure 2

1.5

1.5

GHz

Output Rise/Fall

Time (20% to 80%)

tR, tF Figure 2

80

120 90

130 90

145 ps

Note 1: Measurements are made with the device in thermal equilibrium.

Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative.

Note 3: DC parameters are production tested at TA = +25°C and guaranteed by design over the full operating temperature range.

Note 4: Use VBB only for inputs that are on the same device as the VBB reference.

Note 5: All pins are open except VCC and VEE.

Note 6: Guaranteed by design and characterization. Limits are set at ±6 sigma.

Note 7: Measured between outputs of the same part at the signal crossing points for a same-edge transition.

Note 8: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition.

Note 9: Device jitter added to a jitter-free input signal.

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