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SST38VF166-70-4C-EK

16 Megabit FlashBank Memory

Silicon Storage Technology 

The requirements for JEDEC compliant SDP are in byte

format. The SST38VF166 is organized by word; therefore,

the contents of DQ8 to DQ15 are “Don’t Care” during any

SDP (3-word or 6-word) command sequence.

During the SDP load command sequence, the SDP load

cycle is suspended when WE# is high. This means a read

may occur to any other bank during the SDP load

sequence.

The SDP load sequence is bank specific, i.e., the same

BE# must be low for each bus cycle. If the command

sequence is aborted, e.g., a different BE# is brought low

(except for Read operation with WE# high), an incorrect

address is loaded, or incorrect data is loaded, the device

will return to the Read mode within TRC of execution of the

load error.

Concurrent Read and Write Operations

The SST38VF166 provides the unique benefit of being

able to read any bank, while simultaneously writing, eras-

ing, or programming one other bank. This allows data alter-

ation code to be executed from one bank, while altering the

data in another bank. The following table lists all valid

states.

TABLE 1: CONCURRENT READ/WRITE STATE

Flash Bank 1

Flash Bank 2

E2 Bank

Read

No Operation

Write

Read

Write

No Operation

Write

Read

No Operation

No Operation

Read

Write

Write

No Operation

Read

No Operation

Write

Read

T1.0 327

Note: For the purposes of this table, write means to Word-Write;

Block-, Sector-, or Chip-Erase; or Word-Program as applica-

ble to the appropriate bank.

SST does not recommend that any two of the bank enable

signals BE#1, BE#2 or BE#3 be simultaneously asserted.

The device will ignore all SDP commands and toggling of

WE# when an Erase, Program, or Write operation is in

progress. Note, both Product Identification and the Com-

mon Flash Interface entry commands use SDP; therefore,

these commands will also be ignored while an Erase, Pro-

gram, or Write operation is in progress.

16 Megabit FlashBank Memory

SST38VF166

Data Sheet

Product Identification

The product identification mode identifies the device manu-

facturer as SST and provides a code to identify each bank.

The manufacturer ID is the same for each bank; however,

each bank has a separate device ID. Each bank is individu-

ally accessed using the applicable BE# and a software

command. Users may wish to use the device ID operation

to identify the write algorithm requirements for each bank.

For details, see Table 6 or 7 for software operation and Fig-

ures 27, 28, or 29 for timing waveforms.

TABLE 2: PRODUCT IDENTIFICATION

Manufacturer’s ID

Device ID

Flash Bank 1

Flash Bank 2

E2 Bank

Address

0000H

0001H

0001H

0001H

Data

00BFH

2791H

2792H

2793H

T2.1 327

Device IDs are unique to each bank. Should a chip ID be

required, any of the bank IDs may be used as the chip ID.

While in the read software ID mode or CFI mode, no other

operation is allowed until after exiting these modes.

Product Identification Mode Exit

In order to return to the standard Read mode, the Product

Identification mode must be exited. Exit is accomplished by

issuing the Software ID exit command, which returns the

device to normal operation. This command may also be

used to reset the device to the Read mode after any inad-

vertent transient condition that apparently causes the

device to behave abnormally, e.g., not read correctly. For

details, see Table 6 or 7 for software operation and Figures

30, 31, or 32 for timing waveforms.

©2001 Silicon Storage Technology, Inc.

6

327-3 2/01

S71065

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