INTRODUCTION
The YSS912C is one chip LSI consisting two built-in DSP’s ; Dolby Digital (AC-3) / Pro Logic / DTS decoder (Main DSP) and a sound processing DSP (Sub DSP). Sub DSP is capable of realizing various sound fields, such as virtual surround, by down-loading the program and coefficient. Sub DSP is compatible with YSS902, the Sub DSP programs developed for YSS902 are also applicable to YSS912C.

FEATURERS
• Pin compatible with YSS902 (AC3D).
• Dolby Digital (AC-3) / Pro Logic and DTS decode.
• 24 bit DSP. (Group-A Dolby Digital decoder)
• No external memory is required (Memory for center and surround channel delay is included) when DTS decoding as well as AC-3 / Pro Logic.
• Possible to decode multi-language encoded data. (possible to decode based on data-stream-number)
• AC-3 karaoke mode.
• Original compression mode as well as four compression modes recommended by Dolby. (when AC-3 decoding)
• Included de-emphasis filter.
• Pro Logic decoding for Dolby digital 2 channels decoded signal as well as ordinary PCM.
• High performance 25 MIPS programmable DSP suitable for a variety of sound field processing such as original surround , filtering, virtual surround etc.
• Up to 1.36 second delay time is capable when used with an external 1Mbit SRAM. (at fs= 48 kHz)
• Reads Dolby Digital (AC-3)/DTS decode information through the microprocessor interface.
• Provide total sixteen I/O ports.
• Possible to connect most of SPDIF receivers, A/D and D/A converters, by setting I/O data interface format.
• Has a built-in PLL oscillation circuit to generates its own operating clock.
• Internal operating clock is 30 MHz.
• Supply Voltage: 3.3v for core logic. 5v for I/Os.
• Power saving mode.
• Si-gate CMOS process.
• 100 QFP.(YSS912C-F)