YSS912C 데이터 시트보기 (PDF) - Yamaha Corporation
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YSS912C Datasheet PDF : 14 Pages
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SERIAL DATA INTERFACE
Data timing of the serial data interface is as follows.
Bit clock
(SDBCK0,
SDBCK1)
BP=0
BP=1
Word Clock
(SDWCK0,
SDWCK1)
WP=0
WP=1
Lch (LS, C ch)
Lch (LS, C ch)
YSS912C
Rch (RS, LFE ch)
Rch (RS, LFE ch)
BIT=00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIT=01 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIT=10 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIT=11 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMT=00 (No delay)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIT=00
Data
BIT=01
(SDIA,SDIB,
SDOA,SDOB)
BIT=10
BIT=11
FMT=01 (EIAJ)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIT=00
BIT=01
BIT=10
BIT=11
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMT=10 (I2S)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Please refer to Application manual for details of SDIA, SDOA, SDIB, and SDOB registers.
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