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UJA1078 데이터시트 - NXP Semiconductors.

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UJA1078

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NXP
NXP Semiconductors. NXP

General description
The UJA1078 core System Basis Chip (SBC) replaces the basic discrete components commonly found in Electronic Control Units (ECU) with a high-speed Controller Area Network (CAN) and two Local Interconnect Network (LIN) interfaces.
The UJA1078 supports the networking applications used to control power and sensor peripherals by using a high-speed CAN as the main network interface and the LIN interfaces as local sub-busses.


FEATUREs and benefits
2.1 General
■ Contains a full set of CAN and LIN ECU functions:
   ♦ CAN transceiver and two LIN transceivers
   ♦ Scalable 3.3 V or 5 V voltage regulator delivering up to 250 mA for a microcontroller and peripheral circuitry; an external PNP transistor can be connected for better heat distribution over the PCB
   ♦ Separate voltage regulator for the CAN transceiver (5 V)
   ♦ Watchdog with Window and Timeout modes and on-chip oscillator
   ♦ Serial Peripheral Interface (SPI) for communicating with the microcontroller
   ♦ ECU power management system
■ Designed for automotive applications:
   ♦ Excellent ElectroMagnetic Compatibility (EMC) performance
   ♦ ±8 kV ElectroStatic Discharge (ESD) protection Human Body Model (HBM) on the CAN/LIN bus pins and the WAKE pins
   ♦ ±6 kV ElectroStatic Discharge (ESD) protection IEC 61000-4-2 on the CAN/LIN bus pins and the WAKE pins
   ♦ ±58 V short-circuit proof CAN/LIN bus pins
   ♦ Battery and CAN/LIN bus pins are protected against transients in accordance with ISO 7637-3
■ Supports remote flash programming via the CAN bus
■ Small 6.1 mm × 11 mm HTSSOP32 package with low thermal resistance
■ Pb-free; RoHS and dark green compliant

2.2 CAN transceiver
■ ISO 11898-2 and ISO 11898-5 compliant high-speed CAN transceiver
■ Dedicated low dropout voltage regulator for the CAN bus:
   ♦ Independent of the microcontroller supply
   ♦ Significantly improves EMC performance
■ Bus connections are truly floating when power is off
■ SPLIT output pin for stabilizing the recessive bus level

2.3 LIN transceivers
■ 2 × LIN 2.1 compliant LIN transceivers
■ Compliant with SAE J2602
■ Downward compatible with LIN 2.0 and LIN 1.3
■ Low slope mode for optimized EMC performance
■ Integrated LIN termination diode at pin DLIN

2.4 Power management
■ Wake-up via CAN, LIN or local WAKE pins with wake-up source detection
■ 2 WAKE pins:
■  ♦ WAKE1 and WAKE2 inputs can be switched off to reduce current flow
■  ♦ Output signal (WBIAS) to bias the WAKE pins, selectable sampling time of 16 ms or 64 ms
■ Standby mode with very low standby current and full wake-up capability; V1 active to maintain supply to the microcontroller
■ Sleep mode with very low sleep current and full wake-up capability

2.5 Control and Diagnostic features
■ Safe and predictable behavior under all conditions
■ Programmable watchdog with independent clock source:
■  ♦ Window, Timeout (with optional cyclic wake-up) and Off modes supported (with automatic re-enable in the event of an interrupt)
■ 16-bit Serial Peripheral Interface (SPI) for configuration, control and diagnosis
■ Global enable output for controlling safety-critical hardware
■ Limp home output (LIMP) for activating application-specific ‘limp home’ hardware in the event of a serious system malfunction
■ Overtemperature shutdown
■ Interrupt output pin; interrupts can be individually configured to signal V1/V2 undervoltage, CAN/LIN/local wake-up and cyclic and power-on interrupt events
■ Bidirectional reset pin with variable power-on reset length to support a variety of microcontrollers
■ Software-initiated system reset

2.6 Voltage regulators
■ Main voltage regulator V1:
   ♦ Scalable voltage regulator for the microcontroller, its peripherals and additional external transceivers
   ♦ ±2 % accuracy for LIN master application
   ♦ ±3 % accuracy for LIN slave application
   ♦ 3.3 V and 5 V versions available
   ♦ Delivers up to 250 mA and can be combined with an external PNP transistor for better heat distribution over the PCB
   ♦ Selectable current threshold at which the external PNP transistor starts to deliver current
   ♦ Undervoltage warning at 90 % of nominal output voltage and undervoltage reset at 90 % or 70 % of nominal output voltage
   ♦ Can operate at VBAT voltages down to 4.5 V (e.g. during cranking), in accordance with ISO 7637 pulse 4/4b and ISO16750-2
   ♦ Stable output under all conditions
■ Voltage regulator V2 for CAN transceiver:
   ♦ Dedicated voltage regulator for on-chip high-speed CAN transceiver
   ♦ Undervoltage warning at 90 % of nominal output voltage
   ♦ Can be switched off; CAN transceiver can be supplied by V1 or by an external voltage regulator
   ♦ Can operate at VBAT voltages down to 5.5 V (e.g. during cranking) in accordance with ISO 7637, pulse 4
   ♦ Stable output under all conditions

 

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