UJA1078 데이터 시트보기 (PDF) - NXP Semiconductors.
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UJA1078 Datasheet PDF : 53 Pages
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NXP Semiconductors
UJA1078
High-speed CAN/dual LIN core system basis chip
from Standby or Normal
VBAT below
power-off threshold Vth(det)poff
(from all modes)
Overtemp
V1: OFF
V2: OFF
limp home = LOW (active)
CAN/LIN: Off and
high resistance
watchdog: OFF
chip temperature above
OTP activatrion threshold Tth(act)otp
VBAT below
power-on threshold Vth(det)pon
Off
V1: OFF
V2: OFF
CAN/LIN: Off and
high resistance
watchdog: OFF
INTN: HIGH
chip temperature below
OTP release threshold Tth(rel)otp
VBAT above
power-on threshold Vth(det)pon
watchdog overflow or
V1 undervoltage
Standby
watchdog
trigger
V1: ON
V2: OFF
CAN/LIN: Lowpower/Off
watchdog: Timeout/Off
MC = 00
reset event or
MC = 00
MC = 10 or MC = 11
MC = 01 and
INTN = HIGH and
one wake-up enabled and
no wake-up pending
successful
watchdog
trigger
Normal
V1: ON
V2: ON/OFF
CAN/LIN: Active/Lowpower
watchdog: Window/
Timeout/Off
MC = 1x
Fig 3. UJA1078 system controller
wake-up event if enabled
MC = 01 and
INTN = HIGH and
one wake-up enabled and
no wake-up pending
Sleep
V1: OFF
V2: OFF
CAN/LIN: Lowpower/Off
watchdog: OFF
RSTN: LOW
MC = 01
015aaa073
UJA1078_2
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 27 May 2010
© NXP B.V. 2010. All rights reserved.
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