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R5H30211 데이터시트 - Renesas Electronics

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R5H30211

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Renesas
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Overview
This LSI is a single-chip microcontroller unit (MCU) built around the H8/300H CPU. Four I/O ports, ROM, RAM, EEPROM, a random number generator (RNG), a watchdog timer (WDT), a firewall management unit (FMU), interval timers (TMR1/TMR2), I2C bus interface (IIC2), synchronous serial communication unit (SSU), and a coprocessor are included.
Operating at a maximum 10-MHz internal clock rate, the H8/300H CPU rapidly executes bit manipulation instructions, arithmetic and logic instructions, and data transfer instructions.
The on-chip coprocessor executes modular multiplications (such as ABR-1 modN + kN), which are used to calculate modular exponentiation XY modN, and DES calculation processing at a high speed.


FEATUREs
CPU
H8/300H CPU
Upper compatible with the H8/300 CPU in the object level
Sixteen 16-bit registers (Sixteen 8-bit registers + eight 16-bit registers or Eight 32-bit registers)
• High-speed operation
   - Maximum clock rate: internal clock 10 MHz
   - Add/subtract: 0.20 µs (10 MHz)
   - Multiply/divide: 1.40 µs (10 MHz)
• Streamlined, concise instruction set
   - 16-bit variable instruction length: 2 to 10 bytes
   - arithmetic and logic operations between registers
   - MOV instruction for data transfer between registers and memory
• Maximum 16-Mbyte address space
• Instruction set features
   - 8-, 16-, or 32-bit transfer or arithmetic instructions
   - Unsigned or signed multiply instruction (8 bits × 8 bits and 16 bits × 16 bits)
   - Unsigned or signed divide instruction (16 bits ÷ 8 bits and 32 bits ÷ 16 bits)
   - Bit-accumulator instructions
• Register-indirect specification of bit positions
   - EEPROM write instruction (EEPMOV.B instruction)
   - High-speed block transfer instruction (EEPMOV.W instruction)
  
I/O ports
• Four general-purpose input/output ports (Also used for interrupts)
   Note: When writing to the DDR7 to DDR4 bits, use the MOV instruction instead of the bit
   manipulation instruction.
  
On-chip memory
• EEPROM: 16 kbytes + 2 kbytes (64 bytes × (256 + 32) pages)
   - Writing function by dedicated transfer instruction from CPU
   - Page write (1 byte to 64 bytes) and erase
   - Protected against accidental writing and erasing
   - Generates an EWE interrupt before an EEPMOV.B instruction is executed
   - On-chip high voltage generation circuit for writing and erasing
   - Built-in oscillator and timer
   - Write/erase time (maximum value): 3 ms (rewrite), 1.5 ms (erase)
   - Rewrite endurance: 1 × 105 times (-20°C to +75°C)
   - Data retention time: 10 years
• ROM: 112 kbytes
• RAM: 4 kbytes (Continue ...)

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