R5H30211 데이터 시트보기 (PDF) - Renesas Electronics
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R5H30211 Datasheet PDF : 19 Pages
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R5H30211
Block Diagram
Figure 1 is a block diagram of this LSI.
Vcc
Vss
Internal address bus
RES
Power-on
reset circuit
CLK
Clock divider/
multiplier
On-chip
oscillator
H8/300H CPU
I/O port
System control
Security logic
RNG
WDT
FMU
Voltagle monitoring circuit
ROM (112 kbytes)
RAM (4 kbytes)
EEPROM (16 kbytes + 2 kbytes)
Interval timer 1
Interval timer 2
Modular multiplication
coprocessor
Register
(512 bytes)
SSU
IIC2
Figure 1 Block Diagram
P4/SCS/IRQ
P3/SSCK/IRQ
P2/SSO/SCL/IRQ
P1/SSI/SDA/IRQ
Internal data bus
REJ03B0259-0110 Rev.1.10 Jun. 05, 2009
Page 4 of 17
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