CP117 데이터시트 - Central Semiconductor
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CP117
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PROCESS DETAILS
Process EPITAXIAL BASE
Die Size 111 X 111 MILS
Die Thickness 10 MILS
Base Bonding Pad Area 20 X 30 MILS
Emitter Bonding Pad Area 20 X 26 MILS
Top Side Metalization Al - 30,000Å
Back Side Metalization Au/Cr/Ni/Au - Ni-6,000Å, Au-6,000Å
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Power Transistors NPN - Silicon Darlington Transistor Chip ( Rev : 2005 )
Central Semiconductor
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