Description
CD4071BMS, CD4072BMS and CD4075BMS OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates.
The CD4071BMS, CD4072BMS and CD4075BMS are supplied in these 14 lead outline packages:

FEATUREs
• High-Voltage Types (20V Rating)
• CD4071BMS Quad 2-Input OR Gate
• CD4072BMS Dual 4-Input OR Gate
• CD4075BMS Triple 3-Input OR Gate
• Medium Speed Operation:
- tPHL, tPLH = 60ns (typ) at 10V
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25^oC
• Standardized Symmetrical Output Characteristics
• Noise Margin (Over Full Package Temperature Range):
  - 1V at VDD = 5V
  - 2V at VDD = 10V
  - 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices”