CD4071BMS 데이터 시트보기 (PDF) - Intersil

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CD4071BMS

CMOS OR Gate

Intersil 

CD4071BMS, CD4072BMS, CD4075BMS

Chip Dimensions and Pad Layouts

CD4071BMS

CD4072BMS

CD4075BMS

Dimensions in parentheses are in millimeters and are

derived from the basic inch dimensions as indicated.

Grid graduations are in mils (10-3 inch)

METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.

PASSIVATION: 10.4kÅ - 15.6kÅ, Silane

BOND PADS: 0.004 inches X 0.004 inches MIN

DIE THICKNESS: 0.0198 inches - 0.0218 inches

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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate

and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which

may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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