The ADS6608A4Aare four-bank Synchronous DRAMsorganized as 2,097,152 words x8 bitsx4 banks.
Synchronous design allowsprecise cycle control with the use of system clock I/Otransactions are possible on everyclock cycle.

Range of operating frequencies, programmable burst length and programmable latencies allowthe
same device to be useful for a varietyof high bandwidth high performance memorysystem applications

* JEDECstandard LVTTL3.3V power supply
* MRS Cycle with address keyprograms
   - CAS Latency(2 & 3)
   - Burst Length (1,2,4,8,& full page)
  - Burst Type (sequential & Interleave)
* 4 banks operation
* All inputs are sampled at the positive edge of the system clock
* Burst Read single write operation
* Auto & Self refresh
* 4096 refresh cycle
* DQMformasking
* Package:54-pins 400 mil TSOP-Type II