The 54HSC/T630 is a 16-bit parallel Error Detection and Correction circuit. It uses a modified Hamming code to generate a 6-bit check word from each 16-bit data word. The check word is stored with the data word during a memory write cycle. During a memory read cycle a 22-bit word is taken from memory and checked for errors.
Single bit errors in data words are flagged and corrected. Single bit errors in check words are flagged but not corrected. The position of the incorrect bit is pinpointed, in both cases, by the 6-bit error syndrome code which is output during the error correction cycle

FEATURES
■ Radiation Hard:
   Dose Rate Upset Exceeding 3x1010 Rad(Si)/sec
   Total Dose for Functionality Upto 1x106 Rad(Si)
■ High SEU Immunity, Latch Up Free
■ CMOS-SOS Technology
■ All Inputs and Outputs Fully TTL Compatible (54HST630) or CMOS Compatible (54HSC630)
■ Low Power
■ Detects and Corrects Single-Bit Errors
■ Detects and Flags Dual-Bit Errors
■ High Speed:
   Write Cycle - Generates Checkword In 40ns Typical
   Read Cycle - Flags Errors In 20ns Typical