NJU3962E2 데이터 시트보기 (PDF) - Japan Radio Corporation
부품명
상세내역
일치하는 목록
NJU3962E2 Datasheet PDF : 11 Pages
| |||
NJU39612
s DEFINITION OF TERMS
Resolution
Resolution is defined as the reciprocal of the number of discrete steps in the DAC output. It is directly related to the
number of switches or bits within the DAC. For example, NJU39612 has 27, or 128, output levels and therefor has 7
bits resolution. Remember that this is not equal to the number of microsteps available.
Linearity Error
Linearity error is the maximum deviation from a straight line passing through the end points of the DAC transfer
characteristic. It is measured after adjusting for zero and full scale. Linearity error is a parameter intrinsic to the
device and cannot be externally adjusted.
Power Supply Sensitivity
Power supply sensitivity is a measure of the effect of power supply changes on the DAC full-scale output.
Settling Time
Full-scale current settling time requires zero-to-full-scale or full-scale-to-zero output change. Settling time is the
time required from a code transition until the DAC output reaches within ±1/2LSB of the final output value.
Full-scale Error
Full-scale error is a measure of the output error between an ideal DAC and the actual device output.
Differential Non-linearity
The difference between any two consecutive codes in the transfer curve from the theoretical 1LSB, is differential
non-linearity
Monotonic
If the output of a DAC increases for increasing digital input code, then the DAC is monotonic. A 7-bit DAC which is
monotonic to 7 bits simply means that increasing digital input codes will produce an increasing analog output.
NJU39612 is monotonic to 7 bits.
s FUNCTIONAL DESCRIPTION
Each DAC channel contains one register and a D/A converter. A block diagram is shown on the first page.
The sign outputs generate the phase shifts, i.e., they reverse the current direction in the phase windings.
Data Bus Interface
NJU39612 is designed to be compatible with 8-bit microprocessors such as the 6800, 6801, 6803, 6808, 6809,
8051, 8085, Z80 and other popular types and their 16/32 bit counter parts in 8 bit data mode. The data bus inter-
face consists of 8 data bits, write signal, chip select, and two address pins. All inputs are TTL-compatible (except
reset). The address pin control data transfer to the two internal D-type registers. Data is transferred according to
figure 7 and on the positive edge of the write signal.
Output
Output
More
than 2
bits
Less
than 2
bits
Negative
difference
Positive
difference
Input
Input
Figure 3. Errors in D/A conversion. Figure 4. Errors in D/A conversion.
Differential non-linearity of more than Differential non-linearity of less than
1 bit, output is non-monotonic.
1 bit, output is monotonic.
Output
Actual
Gain
error
Correct
Endpoint
non-linearity
Offset error
Full scale Input
Figure 5. Errors in D/A conversion.
Non-linearity, gain and offset errors.
Share Link: 