UT52L1616MC-10 데이터 시트보기 (PDF) - Utron Technology Inc

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UT52L1616MC-10

1M X 16 BIT SDRAM

Utron Technology Inc 



UTRON

Preliminary Rev. 0.91

UT52L1616

1M X 16 BIT SDRAM

Write Terminated by Read

A Read command terminates the previous write command and the new burst read will start as shown. In case of

tCCD=1, CL=3, and tDQZ=2, there is no loss of data bandwidth even if DQM is activated to mask the write data

.

The Burst Stop Command is defined by having RAS and CAS high with, CAS and WE low at the rising edge

of the clock. When using the Burst Stop Command during a burst read cycle, it should be issued x cycles before

the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one.

When using the Burst Stop Command during a burst write cycle, the input data applied coincident with the Burst

Stop Command will be ignored. The last data written (provided that DQM is low at that time) will be the input data

applied one clock previous to the Burst Stop Command.

Precharge-Bank

If a Precharge-Bank command (to bank(k)) is detected by SDRAM component in CLK(n), then there can be no

commands presented to this bank until CLK(n+tRP).

Precharge-All

If a Precharge-All command is detected by SDRAM component in CLK(n), then there can be no commands

presented to this component until CLK(n+tRP).

Read-Auto Precharge

If a Read with Auto-Precharge command (to bank(k)) is detected by SDRAM component in CLK(n), then there can

be no commands presented to this bank until CLK(n+CL+BL-2+tRP).

Write-Auto Precharge

If a Write with Auto-Precharge command (to bank(k)) is detected by SDRAM component in CLK(n), then there can

be no commands presented to this bank until CLK(n+BL+tDAL-1).

Back to back command with Auto precharge

Read or write burst initiated with auto precharge (A10=high during read or write) will execute the read or write

normally with the exception that after the burst operation is over the accessed bank will start precharge. To access

the bank again the user must reactivate with an active bank command.

The commands initiated with auto-precharge cannot be terminated with any other commands for that bank.

Auto Refresh (REF) Command

An auto refresh (REF) refreshes the SDRAM array. Refresh addresses are generated internally by the SDRAM

device and incremented after each auto refresh automatically. No commands (including another auto refresh) can

be issued until a minimum tRC is satisfied.

Self Refresh Entry/Exit

The self refresh mode is entered by holding CE , CAS , RAS ,CKE low and WE high at the rising edge of the

clock. Once the SDRAM enters the Self Refresh mode, all inputs except CKE will be in a don’t care state and

outputs will be tri-stated. The external clock may be halted while the device is in Self Refresh mode, however, the

clock must be restarted 200 cycles before CKE is high. The self refresh command is exited by asserting CKE high.

A new command may be given tRC clocks after CKE is high.

Multi-bank Operation

The following table specifies some of the timing parameters used for the timing diagrams. CL, tRCD and tRP can all

have values of 2 or 3.

CL

CAS latency

3 clocks

BL

Burst Length

4

tRP

RAS Precharge

3 clocks

tRAS

RAS active time

5 clocks

tRCD

RAS to CAS delay

3 clocks

UTRON TECHNOLOGY INC.

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882 FAX: 886-3-5777919

16

P90004

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