UT52L1616MC-10 데이터 시트보기 (PDF) - Utron Technology Inc

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UT52L1616MC-10

1M X 16 BIT SDRAM

Utron Technology Inc 



UTRON

Preliminary Rev. 0.91

UT52L1616

1M X 16 BIT SDRAM

Multi-bank ping pong access

Two-bank Ping-Pong accesses are described in the following diagram. Another bank can be activated while the

first bank is being accessed as shown. RAS to RAS delay tRRD must be met while activating another bank.

Read and Write with Autoprecharge

Burst reads and writes with auto precharge commands are initiated with Autoprecharge if A10 is at a high state

while the read or write commands are issued.

Precharge Termination of Burst

Burst reads and writes without Autoprecharge can be terminated prematurely by a precharge command. If the

burst read or write command was issued in auto precharge mode then the commands may not be terminated

prematurely for that bank.

Precharge Command After a Burst Read

The earliest a precharge command can be issued after a Read command without the loss of data is CL + BL – 2

clocks. The precharge command can be issued as soon as the tRAS time is met. The earliest time that precharge

can be issued is shown for the CAS Latency = 3 device.

Precharge Termination of a Burst Read

Burst Read (with no Autoprecharge) can be terminated earlier using a precharge command along with the DQM .

It allows starting the precharge early. The remaining data is undefined. DQM should be used to mask the invalid

data.

Precharge Termination of a Burst Write

To terminate Burst Write early with precharge command the DQM signal must be used as shown. Data sampled

tRDL clocks before precharge command will be written correctly. Data sampled afterward and before the precharge

command is undefined. DQM must be used to prevent the location from being corrupted. DQM must be asserted

active to prevent location (A3 and A4 in this case) from being corrupted. DQ(A2) will be written correctly as tRDL is

met.

Read Terminated by Read

A Read command will terminate the previous read command and the data will be available after CAS Latency for

the new command. Fastest command to command delay is determined by tCCD (1 clock as shown).

Write Terminated by Write

A Write command will terminate the previous write command and the new burst write command will start with the

new command as shown. Fastest command to command delay is determined by tCCD (1 clock as shown).

Read Terminated by Write

A Write command terminates the previous read command and the new burst write will start . The minimum

command delay for valid operation (i.e. read-modified-write) = CAS Latency + 2. The DQM must be held active for

3 clocks to keep the output buffer in Hi-Z as shown to prevent an internal IO buffer conflict between the read data

(in pipe) and the write data driven on the input pins.

SDRAM commands to two banks in consecutive clocks

Given COMMAND1 detected by SDRAM component (to bank(i)), it will handle correctly COMMAND2 (to bank(j))

that is detected in the next clock or later clock.

Also, note that COMMAND1 (or COMMAND2) can be: Precharge-Bank, Internally-Scheduled_Auto-Precharge,

Activate, Read or Write. Command1/2 cannot be a Precharge-All. Next command to same bank after Precharge

UTRON TECHNOLOGY INC.

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882 FAX: 886-3-5777919

15

P90004

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