CY7C1464AV33 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C1464AV33
Cypress Semiconductor
CY7C1464AV33 Datasheet PDF : 27 Pages
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CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
counter is incremented. The correct BW (BWa,b,c,d,e,f,g,h for
CY7C1464AV33, BWa,b,c,d for CY7C1460AV33 and BWa,b for
CY7C1462AV33) inputs must be driven in each cycle of the
burst write in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive
for the duration of tZZREC after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
Second
Address
Third
Address
A1,A0
A1,A0
A1,A0
00
01
10
01
00
11
10
11
00
11
10
01
Fourth
Address
A1,A0
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1,A0
00
01
10
11
Second
Address
A1,A0
01
10
11
00
Third
Address
A1,A0
10
11
00
01
Fourth
Address
A1,A0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
Test Conditions
ZZ > VDD − 0.2V
ZZ > VDD − 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Truth Table[1, 2, 3, 4, 5, 6, 7]
Operation
Deselect Cycle
Address
Used
CE ZZ ADV/LD WE BWx OE CEN
None
H
L
L
X
X
X
L
Continue
Deselect Cycle
None
X
L
H
X
X
X
L
Read Cycle
(Begin Burst)
External L
L
L
H
X
L
L
Read Cycle
(Continue Burst)
Next
X
L
H
X
X
L
L
NOP/Dummy Read External L
L
L
H
X
H
L
(Begin Burst)
Dummy Read
(Continue Burst)
Next
X
L
H
X
X
H
L
Min.
2tCYC
0
Max.
100
2tCYC
2tCYC
Unit
mA
ns
ns
ns
ns
CLK
L-H
L-H
L-H
L-H
L-H
L-H
DQ
Tri-State
Tri-State
Data Out (Q)
Data Out (Q)
Tri-State
Tri-State
Notes:
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx =
Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BWX. See Write Cycle Description table for details.
3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQs and DQPX = Tri-state when OE
is inactive or when the device is deselected, and DQs=data when OE is active.
Document #: 38-05353 Rev. *D
Page 8 of 27
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