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CY7C1464AV33

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL™ Architecture

Cypress Semiconductor

CY7C1464AV33 Datasheet PDF : 27 Pages

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Pin Definitions (continued)

Pin Name

CLK

CE1

CE2

CE3

CEN

DQa

DQb

DQc

DQd

DQe

DQf

DQg

DQh

DQPa,DQPb,

DQPc,DQPd

DQPe,DQPf

DQPg,DQPh

MODE

TDO

TDI

TMS

TCK

VDD

VDDQ

VSS

NC/72M

NC/144M

NC/288M

NC/576M

NC/1G

I/O Type

Pin Description

Input-

Clock

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with

CEN. CLK is only recognized if CEN is active LOW.

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

Input-

Asynchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

with CE2 and CE3 to select/deselect the device.

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in

conjunction with CE1 and CE3 to select/deselect the device.

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

with CE1 and CE2 to select/deselect the device.

Output Enable, active LOW. Combined with the synchronous logic block inside the device

to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as

outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is

masked during the data portion of a write sequence, during the first clock when emerging

from a deselected state and when the device has been deselected.

Input-

Synchronous

Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by

the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN

does not deselect the device, CEN can be used to extend the previous cycle when required.

I/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is

triggered by the rising edge of CLK. As outputs, they deliver the data contained in the

memory location specified by AX during the previous clock rise of the read cycle. The

direction of the pins is controlled by OE and the internal control logic. When OE is asserted

LOW, the pins can behave as outputs. When HIGH, DQa–DQd are placed in a tri-state

condition. The outputs are automatically tri-stated during the data portion of a write

sequence, during the first clock when emerging from a deselected state, and when the

device is deselected, regardless of the state of OE.

I/O-

Synchronous

Input Strap Pin

Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[31:0].

During write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is

controlled by BWc, and DQPd is controlled by BWd, DQPe is controlled by BWe, DQPf is

controlled by BWf, DQPg is controlled by BWg, DQPh is controlled by BWh.

Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst

order. Pulled LOW selects the linear burst order. MODE should not change states during

operation. When left floating MODE will default HIGH, to an interleaved burst order.

JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.

Synchronous

JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.

Synchronous

Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of

Synchronous TCK.

JTAG-Clock Clock input to the JTAG circuitry.

Power Supply Power supply inputs to the core of the device.

I/O Power Supply Power supply for the I/O circuitry.

Ground

N/A

Ground for the device. Should be connected to ground of the system.

No connects. This pin is not connected to the die.