ADSP-21367BBP-2A 데이터 시트보기 (PDF) - Analog Devices
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ADSP-21367BBP-2A Datasheet PDF : 56 Pages
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ADSP-21367/ADSP-21368/ADSP-21369
Clock Input
Table 14. Clock Input
400 MHz
Parameter
Min
Max
Timing Requirements
tCK
tCKL
tCKH
tCKRF
t2
CCLK
t 3, 4
CKJ
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V to 2.0 V)
CCLK Period
CLKIN Jitter Tolerance
151
7.51
7.51
2.51
–250
100
45
45
3
10
+250
1 Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in PMCTL.
2 Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK.
3 Actual input jitter should be combined with ac specifications for accurate timing analysis.
4 Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.
333 MHz
Min
Max
181
91
91
3.01
–250
100
45
45
3
10
+250
266 MHz
Min
Max
22.51
11.251
11.251
3.751
–250
100
45
45
3
10
+250
Unit
ns
ns
ns
ns
ns
ps
CLKIN
tCKH
tCK
tCKL
Figure 6. Clock Input
Clock Signals
The processors can use an external clock or a crystal. See the
CLKIN pin description in Table 5 on Page 12. Programs can
configure the processor to use its internal clock generator by
connecting the necessary components to CLKIN and XTAL.
Figure 7 shows the component connections used for a crystal
operating in fundamental mode.
Note that the clock rate is achieved using a 25 MHz crystal and a
PLL multiplier ratio 16:1 (CCLK:CLKIN achieves a clock speed
of 400 MHz). To achieve the full core clock rate, programs need
to configure the multiplier bits in the PMCTL register.
tCKJ
CLKIN
C1
22pF
ADSP-2136x
R1
1M⍀*
Y1
25.00 MHz
XTAL
R2
47⍀*
C2
22pF
R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL
DRIVE POWER. REFER TO CRYSTAL
MANUFACTURER’S SPECIFICATIONS
*TYPICAL VALUES
Figure 7. 400 MHz Operation (Fundamental Mode Crystal)
Rev. C | Page 20 of 56 | January 2008
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