ADSP-21367BBP-2A 데이터 시트보기 (PDF) - Analog Devices

부품명

상세내역

일치하는 목록

ADSP-21367BBP-2A

SHARC Processors

Analog Devices 

Table 5. Pin List

Name

SDWE

SDCKE

SDA10

Type

O/T (pu)1

O/T (pu)1

O/T (pu)1

SDCLK0

O/T

SDCLK1

O/T

State During/

After Reset

(ID = 00x)

Pulled high/

driven high

Pulled high/

driven high

Pulled high/

driven low

High-Z/driving

MS0–1

O/T (pu)1

Pulled high/

driven high

FLAG[0]/IRQ0

I/O

FLAG[1]/IRQ1

I/O

FLAG[2]/IRQ2/

MS2

FLAG[3]/TIMEXP/

MS3

TDI

I/O with programmable

pu (for MS mode)

I/O with programmable

pu (for MS mode)

I (pu)

TDO

O/T

TMS

I (pu)

TCK

I

High-Z/high-Z

High-Z/high-Z

High-Z/high-Z

High-Z/high-Z

TRST

I (pu)

EMU

O/T (pu)

ADSP-21367/ADSP-21368/ADSP-21369

Description

SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin.

SDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the

CLK signal. For details, see the data sheet supplied with the SDRAM device.

SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with non-

SDRAM accesses. This pin replaces the DSP’s A10 pin only during SDRAM

accesses.

SDRAM Clock Output 0. Clock driver for this pin differs from all other clock

drivers. See Figure 38 on Page 46.

SDRAM Clock Output 1. Additional clock for SDRAM devices. For systems with

multiple SDRAM devices, handles the increased clock load requirements, elimi-

nating need of off-chip clock buffers. Either SDCLK1 or both SDCLKx pins can be

three-stated. Clock driver for this pin differs from all other clock drivers. See

Figure 38 on Page 46.

The SDCLK1 signal is only available on the SBGA package. SDCLK1 is not available

on the LQFP_EP package.

Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the

corresponding banks of external memory. The MS3-0 lines are decoded memory

address lines that change at the same time as the other address lines. When no

external memory access is occurring, the MS3-0 lines are inactive; they are active,

however, when a conditional memory access instruction is executed, whether or

not the condition is true.

The MS1 pin can be used in EPORT/FLASH boot mode. See the hardware reference

for more information.

FLAG0/Interrupt Request 0.

FLAG1/Interrupt Request 1.

FLAG2/Interrupt Request 2/Memory Select 2.

FLAG3/Timer Expired/Memory Select 3.

Test Data Input (JTAG). Provides serial data for the boundary scan logic.

Test Data Output (JTAG). Serial scan output of the boundary scan path.

Test Mode Select (JTAG). Used to control the test state machine.

Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted

(pulsed low) after power-up, or held low for proper operation of the processor

Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed

low) after power-up or held low for proper operation of the processor.

Emulation Status. Must be connected to the ADSP-21367/ADSP-21368/

ADSP-21369 Analog Devices DSP Tools product line of JTAG emulator target

board connectors only.

Rev. C | Page 13 of 56 | January 2008

Share Link: