ADSP-21367BBP-2A 데이터 시트보기 (PDF) - Analog Devices

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ADSP-21367BBP-2A

SHARC Processors

Analog Devices 

ADSP-21367/ADSP-21368/ADSP-21369

Power-Up Sequencing

The timing requirements for processor start-up are given in

Table 13.

Table 13. Power-Up Sequencing Timing Requirements (Processor Start-up)

Parameter

Min

Max

Unit

Timing Requirements

tRSTVDD

RESET Low Before V /V DDINT DDEXT On

0

tIVDDEVDD

VDDINT On Before VDDEXT

–50

t1

CLKVDD

CLKIN Valid After V /V DDINT DDEXT Valid

0

tCLKRST

CLKIN Valid Before RESET Deasserted

102

tPLLRST

PLL Control Setup Before RESET Deasserted

20

Switching Characteristic

ns

+200 ms

200

ms

μs

μs

tCORERST

Core Reset Deasserted After RESET Deasserted

4096tCK + 2 tCCLK 3, 4

1 Valid V /V DDINT DDEXT assumes that the supplies are fully ramped to their 1.2 V rails and 3.3 V rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds

depending on the design of the power supply subsystem.

2 Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for start-up time.

Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

3 Applies after the power-up sequence is complete. Subsequent resets require RESET to be held low a minimum of four CLKIN cycles in order to properly initialize and propagate

default states at all I/O pins.

4 The 4096 cycle count depends on tsrst specification in Table 15. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097 cycles

maximum.

RESET

VDDINT

VDDEXT

CLKIN

CLK_CFG1-0

RESETOUT

tRSTVDD

tIVDDEVDD

tCLKVDD

tCLKRST

tPLLRST

Figure 5. Power-Up Sequencing

tCO RERST

Rev. C | Page 19 of 56 | January 2008

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