UT51C164MC-25 데이터 시트보기 (PDF) - Utron Technology Inc

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UT51C164MC-25

256K X 16 BIT EDO DRAM

Utron Technology Inc 



UTRON

UT51C164

Rev 1.5

256K X 16 BIT EDO DRAM

Notes:

1. tRCD (Max.) is specified for reference only. Operation within tRCD (Max.) limits insures that tRAC

(Max.) and tCAA (Max.) can be met. If tRCD is greater than the specified tRCD (Max.), the access

time is controlled by tCAA and tCAC.

2. Either tRRH or tRCH must be satisfied for Read Cycle to occur.

3. Measured with a load equivalent to one TTL input and 50pF.

4. Access time is determined by the longest of tCAA , tCAC and tCAP .

5. Assumes that tRAD ≦ tRAD (Max.). If tRCD is greater than tRCD (Max.), tRAC will increase by the

amount that tRCD exceeds tRCD (Max.)

6. Assumes that tRCD ≦ tRCD (Max.). If tRCD is greater than tRCD (Max.), tRAC will increase by the

amount that tRAD exceeds tRAD (Max.)

7. Assumes that tRAD ≧ tRAD (Max.).

8. Operation within the tRAD (Max.) limits ensures that tRA can be met. tRAD (Max.) is specified as a

reference point only. If tRAD is greater than the specified tRAD (Max.), the access time is controlled

by tCAA and tCAC.

9. tWCS , tRWD , tAWD and tCWD are not restrictive operating parameters.

10. tWCS (min.) must be satisfied in an Early Write Cycle.

11. tDS and tDH are referenced to the latter occurrence of CAS or WE .

12. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 3ns.

13. Assumes a tri-state test load (5pF and a 500Ohm Thevenin equivalent).

14.An initial pause of 200us is required after power-up followed by any 8 CBR or ROR cycles

before device operation is achieved.

UTRON TECHNOLOGY INC.

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882 FAX: 886-3-5777919

9

P90005

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