CS51021A 데이터 시트보기 (PDF) - ON Semiconductor
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CS51021A Datasheet PDF : 11 Pages
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CS51021A, CS51022A, CS51023A, CS51024A
Slope Compensation
DC−DC converters with current mode control require a
current sense signal with slope compensation to avoid
instability at duty cycles greater than 50%. Slope capacitor
CS is charged by an internal 53 mA current source and is
discharged during the oscillator discharge time. The slope
compensation voltage is divided by 10 and is added to the
current sense voltage, VI(SENSE). The signal applied to the
input of the PWM comparator is a combination of these two
voltages. The slope compensation, dVSLOPE/dt, is
calculated using the following formula:
dVSLOPE
dt
+
0.1
53 mA
CS
It should be noted that internal capacitance of the IC will
cause an error when determining slope compensation
capacitance CS. This error is typically small for large values
of CS, but increases as CS becomes small and comparable to
the internal capacitance. The effect is apparent as a reduction
in charging current due to the need to charge the internal
capacitance in parallel with CS.Figure 4 shows a typical
curve indicating this decrease in available charging current.
60
55
50
45
40
35
30
25
20
10
100
Compensation Cap (pF)
1000
Figure 4. The Slope Compensation Pin Charge
Current Reduces When a Small Capacitor Is Used.
Undervoltage (UV) and Overvoltage (OV) Monitor
Two independent comparators monitor OV and UV
conditions. A string of three resistors is connected in series
between the monitored voltage (usually the input voltage)
and ground (see Figure 5). When voltage at the OV pin
exceeds 2.5 V, an overvoltage condition is detected and
GATE shuts down. An internal 12.5 mA current source turns
on and feeds current into the external resistor, R3, creating
a hysteresis determined by the value of this resistor (the
higher the value, the greater the hysteresis). The hysteresis
voltage of the OV monitor is determined by the following
formula:
VOV(HYST) + 12.5 mA R3
where R3 is a resistor connected from the OV pin to ground.
When the monitored voltage is low and the UV pin is less
than 1.45 V, GATE shuts down. The UV pin has fixed 75 mV
hysteresis.
Both OV and UV conditions are latched until the Soft Start
capacitor is discharged. This way, every time a fault
condition is detected the controller goes through the power
up sequence.
R1
R2
R3
VIN
VUV
VOV
Figure 5. UV/OV Monitor Divider
To calculate the OV?UV resistor divider :
1. Solve for R3, based on OV hysteresis requirements.
R3
+
VOV(HYST) 2.5
VMAX 12.5 mA
V
where VOV(HYST) is the desired amount of
overvoltage hysteresis, and VMAX is the input voltage
at which the supply will shut down.
2. Find the total impedance of the divider.
RTOT
+
R1
)
R2
)
R3
+
VMAX
2.5
R3
3. Determine the value of R2 from the UV threshold
conditions.
R2
+
1.45 RTOT
VMIN
*
R3
where VMIN is the UV voltage at which the supply
will shut down.
4. Calculate R1.
R1 + RTOT * R2 * R3
5. The undervoltage hysteresis is given by :
VUV(HYST)
+
VMIN 0.075
1.45
VREF Monitor
The 5.0 V reference voltage is internally monitored to
ensure that it remains within specifications. The monitor,
which outputs a fault, can be tripped by two methods:
• If the reference voltage drops below 4.75 V
• If VCC falls below the STOP threshold
As indicated in the block diagram, any fault causes the
output to stop switching and begins the discharge of the Soft
Start capacitor CSS.
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