CS51021A 데이터 시트보기 (PDF) - ON Semiconductor

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CS51021A

Enhanced Current Mode PWM Controller

ON Semiconductor 

CS51021A, CS51022A, CS51023A, CS51024A

CIRCUIT DESCRIPTION

200 ns

4.3 V

TCH

0V

VSLOPE

TDIS

0V

0V

IS + 0.1 SLOPE

IS

0V

0V

55 ns

Blanking

SYNC

RTCT

SLOP

E

IS

VCOMP

PWM COMP

GATE

VDS

VIN

0V

Figure 3. Typical Waveforms

THEORY OF OPERATION

Powering the IC

The IC has two supply and two ground pins. VC and

PGND pins provide high speed power drive for the external

power switch. VCC and LGND pins power the control

portion of the IC. The internal logic monitors the supply

voltage, VCC. During abnormal operating conditions, the

output is held low. The CS51021A/2A/3A/4A requires only

75 mA of startup current.

Voltage Feedback

The output voltage is monitored via the VFB pin and is

compared with the internal 2.5 V reference. The error

amplifier output minus one diode drop is divided by 3 and

connected to the negative input of the PWM comparator.

The positive input of the PWM comparator is connected to

the modified current sense signal. The oscillator turns the

external power switch on at the beginning of each cycle.

When current sense ramp voltage exceeds the reference side

of PWM comparator, the output stage latches off. It is turned

on again at the beginning of the next oscillator cycle.

Current Sense and Protection

The current is monitored at the ISENSE pin. The

CS51021A/2A/3A/4A has leading edge blanking circuitry

that ignores the first 55 ns of each switching period.

Blanking is disabled when VFB is less than 2.0 V so that the

minimum on−time of the controller does not have an

additional 55 ns of delay time during fault conditions. For

the remaining portion of the switching period, the current

sense signal, combined with a fraction of the slope

compensation voltage, is applied to the positive input of the

PWM comparator where it is compared with the divided by

three error amplifier output voltage. The pulse−by−pulse

overcurrent protection threshold is set by the voltage at the

ISET pin. This voltage is passed through the ISET Clamp and

appears at the non−inverting input of the PWM comparator,

limiting its dynamic range according to the following

formula:

Overcurrent Threshold + 0.8 VI(SENSE)

) 0.1 V ) 0.1 VSLOPE

where

VI(SENSE) is voltage at the ISENSE pin.

and

VSLOPE is voltage at the SLOPE pin.

During extreme overcurrent or short circuit conditions,

the slope of the current sense signal will become much

steeper than during normal operation. Due to loop

propagation delay, the sensed signal will overshoot the

pulse−by−pulse threshold eventually reaching the second

overcurrent protection threshold which is 1.33 times higher

than the first threshold and is described by the following

equation:

2nd Threshold + 1.33 VI(SET)

Exceeding the second threshold will reset the Soft Start

capacitor CSS and reinitiate the Soft Start sequence,

repeating for as long as the fault condition persists.

Soft Start

During power up, when the output filter capacitor is

discharged and the output voltage is low, the voltage across

the Soft Start capacitor (VSS) controls the duty cycle. An

internal current source of 55 mA charges CSS. The maximum

error amplifier output voltage is clamped by the SS Clamp.

When the Soft Start capacitor voltage exceeds the error

amplifier output voltage, the feedback loop takes over the

duty cycle control. The Soft Start time can be estimated with

the following formula:

tSS + 9 104 CSS

The Soft Start voltage, VSS, charges and discharges

between 0.25 V and 4.7 V.

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