CS51021A 데이터 시트보기 (PDF) - ON Semiconductor

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CS51021A

Enhanced Current Mode PWM Controller

ON Semiconductor 

CS51021A, CS51022A, CS51023A, CS51024A

ELECTRICAL CHARACTERISTICS (Unless otherwise stated, specifications apply for −40°C < TA < 85°C, −40°C < TJ < 150°C,

3.0 V < VC < 20 V, 8.2 V < VCC < 20 V, RT = 12 kW, CT = 390 pF)

Characteristic

Test Conditions

Min

Typ

Max

Unit

Current Sense

OFFSET Voltage

(Note 4)

0.09

0.10

0.11

V

Blanking Time

−

−

55

160

ns

Blanking Disable Voltage

Adjust VFB

Second Current Threshold Gain

−

1.8

2.0

1.21

1.33

2.2

V

1.45

V/V

ISENSE Input Resistance

Minimum On Time

−

GATE High to Low

−

5.0

−

kW

30

70

110

ns

Gain

(Note 4)

0.78

0.80

0.82

V/V

OV & UV Voltage Monitors

OV Monitor Threshold

−

2.4

2.5

2.6

V

OV Hysteresis Current

−

−10

−12.5

−15

mA

UV Monitor Threshold

−

1.38

1.45

1.52

V

UV Monitor Hysteresis

−

25

75

100

mV

SOFT START (SS)

Charge Current

SS = 2.0 V

−70

−55

−40

mA

Discharge Current

SS = 2.0 V

250

1000

−

mA

Charge Voltage, VSS

−

Discharge Voltage, VSS

−

4. Guaranteed by design, not 100% tested in production.

4.4

4.7

0.25

0.27

5.0

V

0.30

V

PACKAGE PIN DESCRIPTION

PIN #

PIN SYMBOL

FUNCTION

16 Lead SO Narrow

1

GATE

External power switch driver with 1.0 A peak capability.

2

ISENSE

Current sense amplifier input.

3

SYNC (CS51021A/3A) Bi−directional synchronization. Locks to the highest frequency.

3

SLEEP (CS51022A/4A) Active high chip disable. In sleep mode, VREF and GATE are turned off.

4

SLOPE

Additional slope to the current sense signal. Internal current source charges the external capacitor.

5

UV

Undervoltage protection monitor.

6

OV

Overvoltage protection monitor.

7

RTCT

Timing resistor RT and capacitor CT determine oscillator frequency and maximum duty cycle, DMAX.

8

ISET

Voltage at this pin sets pulse−by−pulse overcurrent threshold, and second threshold (1.33 times

higher) with Soft Start retrigger (hiccup mode).

9

VFB

Feedback voltage input. Connected to the error amplifier inverting input.

10

COMP

Error amplifier output. Frequency compensation network is usually connected between COMP and

VFB pins.

Charging external capacitor restricts error amplifier output voltage during the start or fault

11

SS

conditions (hiccup).

12

LGND

Logic ground.

13

VREF

5.0 V reference voltage output.

14

VCC

Logic supply voltage.

15

PGND

Output power stage ground connection.

16

VC

Output power stage supply voltage.

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