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SSTV16859

2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM

Philips Electronics 

Philips Semiconductors

2.5 V 13-bit to 26-bit SSTL_2

registered buffer for stacked DDR DIMM

Product data

SSTV16859

56-TERMINAL CONFIGURATION

Q7A 1

Q6A 2

Q5A 3

Q4A 4

Q3A 5

Q2A 6

Q1A 7

Q13B 8

VDDQ 9

Q12B 10

Q11B 11

Q10B 12

Q9B 13

Q8B 14

42 D10

41 D9

40 D8

39 D7

38 RESET

37 GND

36 CLK

35 CLK

34 VDDQ

33 VDDI

32 VREF

31 D6

30 D5

29 D4

SW01040

TERMINAL DESCRIPTION

TERMINAL

NUMBER

SYMBOL

NAME AND FUNCTION

1, 2, 3, 4, 5, 6,

7, 50, 51, 52,

53, 54, 56

Q13A–Q1A Data output

10, 11, 12, 13,

14, 15, 16, 18,

19, 20, 21, 22

Q13B–Q1B Data output

9, 17, 23, 27,

34, 44, 49, 55

VDDQ

Power supply voltage

26, 33, 45

37, 48

VDDI

GND

Power supply voltage

Ground

24, 25, 28, 29,

30, 31, 39, 40,

41, 42, 43, 46,

47

D1–D13

Data input: clocked in on the

crossing of the rising edge of CK

and the falling edge of CK

32

35, 36

VREF

CK, CK

Input reference voltage

Positive and negative master

clock input

Asynchronous reset input:

51

RESET

resets registers and disables

data and clock differential input

receivers

2002 Feb 19

4

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