SSTV16859 데이터 시트보기 (PDF) - Philips Electronics

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SSTV16859

2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM

Philips Electronics 

Philips Semiconductors

2.5 V 13-bit to 26-bit SSTL_2

registered buffer for stacked DDR DIMM

Product data

SSTV16859

PIN CONFIGURATION

Q13A 1

Q12A 2

Q11A 3

Q10A 4

Q9A 5

VDD 6

GND 7

Q8A 8

Q7A 9

Q6A 10

Q5A 11

Q4A 12

Q3A 13

Q2A 14

GND 15

Q1A 16

Q13B 17

VDD 18

Q12B 19

Q11B 20

Q10B 21

Q9B 22

Q8B 23

Q7B 24

Q6B 25

GND 26

VDD 27

Q5B 28

Q4B 29

Q3B 30

Q2B 31

Q1B 32

64 VDD

63 GND

62 D13

61 D12

60 VDD

59 VDD

58 GND

57 D11

56 D10

55 D9

54 GND

53 D8

52 D7

51 RESET

50 GND

49 CK

48 CK

47 VDD

46 VDD

45 VREF

44 D6

43 GND

42 D5

41 D4

40 D3

39 GND

38 VDD

37 VDD

36 D2

35 D1

34 GND

33 VDD

PIN DESCRIPTION

PIN NUMBER SYMBOL

NAME AND FUNCTION

1, 2, 3, 4, 5, 8,

9, 10, 11, 12,

13, 14, 16

Q13A–Q1A Data output

17, 19, 20, 21,

22, 23, 24, 25,

28, 29, 30, 31,

32

Q13B–Q1B Data output

6, 18, 27, 33,

37, 38, 46, 47,

59, 60, 64

VDD

Power supply voltage

7, 15, 26, 34,

39, 43, 50, 54,

58, 63

GND Ground

35, 36, 40, 41,

42, 44, 52, 53,

55, 56, 57, 61,

62

D1–D13

Data input: clocked in on the

crossing of the rising edge of CK

and the falling edge of CK

45

48, 49

VREF

CK, CK

Input reference voltage

Positive and negative master

clock input

Asynchronous reset input:

51

RESET

resets registers and disables

data and clock differential input

receivers

SW00749

2002 Feb 19

3

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