AD7641BSTZRL 데이터 시트보기 (PDF) - Analog Devices
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AD7641BSTZRL Datasheet PDF : 14 Pages
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Preliminary Technical Data
AD7631/AD7634
Parameter
BUSY High in Master Serial Read after Convert4
CNVST Low to SYNC Asserted Delay (all Modes)
AD7631
AD7634 (Warp Mode/Normal Mode/Impulse Mode)
SYNC Deasserted to BUSY Low Delay
SLAVE SERIAL INTERFACE MODES
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK High
External SCLK Low
Symbol Min
t28
t29
t30
t31
5
t32
1
t33
5
t34
5
t35
12.5
t36
5
t37
5
Typ
Max
See
Table 4
TBD
TBD
25
8
1 In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
2 In warp mode only, the time between conversions is 1 ms; otherwise, there is no required maximum time.
3 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
4 In serial master read during convert mode. See Error! Reference source not found. for serial master read after convert mode timing specifications.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 4. Serial Clock Timings in Master Read After Convert Mode
DIVSCLK[1]
0
0
1
1
DIVSCLK[0]
Symbol
0
1
0
1
Unit
SYNC to SCLK First Edge Delay Minimum
t18
3
17
17
17
ns
Internal SCLK Period Minimum
t19
25
60
120
240
ns
Internal SCLK Period Maximum
t19
40
80
160
320
ns
Internal SCLK High Minimum
t20
12
22
50
100
ns
Internal SCLK Low Minimum
t21
7
21
49
99
ns
SDOUT Valid Setup Time Minimum
t22
4
18
18
18
ns
SDOUT Valid Hold Time Minimum
t23
2
4
30
89
ns
SCLK Last Edge to SYNC Delay Minimum
t24
3
60
140
300
ns
BUSY High Width Maximum (Warp mode)
t28
1.75
2.5
4
7
μs
BUSY High Width Maximum (Normal mode)
t28
2
2.75
4.25
7.25
μs
BUSY High Width Maximum (Impulse mode)
t28
2.25
3
4.5
7.5
μs
Rev. PrC | Page 7 of 14
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