AD7641BSTZRL 데이터 시트보기 (PDF) - Analog Devices
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AD7641BSTZRL Datasheet PDF : 14 Pages
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Preliminary Technical Data
AD7631/AD7634
Pin
No. Mnemonic
24
D13
or RDERROR
25
D14
or HW/SW
26
D15
or SPPDATA
27
D16
or SPPCLK
28
D17
or SPPEN
29
BUSY
30
TEN
31
RD
32
CS
33
RESET
34
PD
35
CNVST
36
BIP
37
REF
Type 1
DO
DI/O
DI/O
DI/O
DI/O
DO
DI
DI
Description
When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high
while SDOUT output is valid.
When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low
while SDOUT output is valid.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 13 of the parallel port data output bus.
When MODE[1:0] = 3 (serial mode), read error. In serial slave mode (EXT/INT = high), this output
is used as an incomplete read error flag. If a data read is started and not completed when the
current conversion is complete, the current data is lost and RDERROR is pulsed high.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 14 of the parallel port data output bus.
When MODE[1:0] = 3 (serial mode) hardware/software select. This input, part of the serial
programmable port, is used to select hardware or software input ranges and mode selection.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 15 of the parallel port data output bus.
When MODE[1:0] = 3 (serial mode), serial programmable port data. This input is used to write in the
serial programmable port data when HW/SW = low.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 16 of the parallel port data output bus.
When MODE[1:0] = 3 (serial mode), serial programmable port clock. This input is used to clock in the
data on SPPDATA. The active edge where the data SPPDATA is updated depends on the logic state of
the INVSCLK pin.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 17 of the parallel port data output bus.
When MODE[1:0] = 3 (serial mode), serial programmable port enable. Asserting this input enables the
serial programmable port.
Busy Output. Transitions high when a conversion is started and remains high until the conversion
is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be
used as a data-ready clock signal.
10 Volt Input Range. Refer to Table 8.
When MODE[1:0] = 0, 1, or 2, this input is used to select the 10V input range.
When MODE[1:0] = 3 (serial mode), and
HW/SW = high, driving TEN high selects the 10 Volt input range.
HW/SW = low, the input range is programmed with the serial programmable port and this pin is a
don’t care.
Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled.
DI
Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled.
CS is also used to gate the external clock in slave serial mode.
DI
Reset Input. When high, resets the ADC. Current conversion, if any, is aborted. Falling edge of
RESET enables the calibration mode indicated by pulsing BUSY high. If not used, this pin can be tied to
DGND.
DI
Power-Down Input. When high, power downs the ADC. Power consumption is reduced and
conversions are inhibited after the current one is completed.
DI
Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state
and initiates a conversion.
DI
Bipolar Input Range. Refer to Table 8.
When MODE[1:0] = 0, 1, or 2, this input is used to select the bipolar input range.
When MODE[1:0] = 3 (serial mode), and
HW/SW = high, driving BIP high selects the bipolar input range.
HW/SW = low, the input range is programmed with the serial programmable port and this pin is a
don’t care.
AI/O Reference Output/Input.
When PDREF/PDBUF = low, the internal reference and buffer are enabled producing 5 V on this pin.
When PDREF/PDBUF = high, the internal reference and buffer are disabled allowing an externally
supplied voltage reference up to AVDD volts. Decoupling is required with or without the internal
reference and buffer.
Rev. PrC | Page 11 of 14
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