ML7029 데이터 시트보기 (PDF) - LAPIS Semiconductor Co., Ltd.

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ML7029

Multifunction ADPCM CODEC

LAPIS Semiconductor Co., Ltd. 

FEDL7029-04

ML7029

PIN FUNCTIONAL DESCRIPTIONS

AIN–, GEX

Transmit analog input and transmit level adjustment.

AIN– is connected to the inverting input of the transmit amplifier. GSX is connected to the transmit amplifier

output. During power-down mode, the GSX output is a high impedance state.

VFRO

Receive analog output. During power-down mode, the VFRO output is in a high impedance state.

SG

Analog signal ground.

The output voltage of this pin is approximately 1.4 V. Put 10 F plus 0.1 F (ceramic type) bypass capacitors

between this pin and AG. During power-down, this output voltage is 0 V. This pin should be used via a buffer if

used externally.

AG

Analog ground.

DG

Digital ground.

This ground is separated from the analog signal ground pin (AG). The DG pin must be kept as close as possible

to AG on the PCB.

Va

Analog +3 V power supply.

VD

Digital +3 V power supply.

This power supply is separated from the analog signal power supply pin (VA). The VD pin must be kept as close

as possible to VA on the PCB.

PDN

Power-down and reset control input.

A “0” level makes the IC enter a power-down state. At the same time, all control register data are reset to the

initial state. Set this pin to “1” during normal operating mode. The power-down state is controlled by a logical

OR with CR0-B5 of the control register. When using PDN for power-down and reset control, set CR0-B5 to

digital “0”. The reset width (a “L” level period) should be 200 ns or more.

Be sure to reset the control registers by executing this power down to keep this pin to digital “0”level for 200 ns

or longer after the power is turned on and VDD exceeds 2.7 V.

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