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HEF4511B 데이터 시트보기 (PDF) - NXP Semiconductors.

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HEF4511B
NXP
NXP Semiconductors. NXP
HEF4511B Datasheet PDF : 20 Pages
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NXP Semiconductors
HEF4511B
BCD to 7-segment latch/decoder/driver
Table 8. Dynamic characteristics …continued
VSS = 0 V; Tamb = 25 C; for test circuit see Figure 8.
Symbol Parameter
Conditions
VDD
tPLH
LOW to HIGH
Dn Qn;
5V
propagation delay see Figure 6
10 V
15 V
LE Qn;
see Figure 6
5V
10 V
15 V
BL Qn;
see Figure 6
5V
10 V
15 V
LT Qn;
see Figure 6
5V
10 V
15 V
tTHL
HIGH to LOW output see Figure 6
5V
transition time
10 V
15 V
tTLH
LOW to HIGH output see Figure 6
5V
transition time
10 V
15 V
tsu
set-up time
Dn LE;
see Figure 7
5V
10 V
15 V
th
hold time
Dn LE;
see Figure 7
5V
10 V
15 V
tW
pulse width
LE input LOW;
minimum width;
see Figure 7
5V
10 V
15 V
Extrapolation formula[1] Min Typ Max Unit
108 ns + (0.55 ns/pF)CL -
135 270 ns
44 ns + (0.23 ns/pF)CL -
55 110 ns
32 ns + (0.16 ns/pF)CL -
40 80 ns
133 ns + (0.55 ns/pF)CL -
160 320 ns
59 ns + (0.23 ns/pF)CL -
70 140 ns
42 ns + (0.16 ns/pF)CL -
50 100 ns
78 ns + (0.55 ns/pF)CL -
105 210 ns
29 ns + (0.23 ns/pF)CL -
40 80 ns
22 ns + (0.16 ns/pF)CL -
30 60 ns
33 ns + (0.55 ns/pF)CL -
60 120 ns
19 ns + (0.23 ns/pF)CL -
30 60 ns
17 ns + (0.16 ns/pF)CL -
25 50 ns
10 ns + (1.00 ns/pF)CL -
60 120 ns
9 ns + (0.42 ns/pF)CL -
30 60 ns
6 ns + (0.28 ns/pF)CL -
20 40 ns
20 ns + (1.00 ns/pF)CL -
25 50 ns
13 ns + (0.06 ns/pF)CL -
16 32 ns
10 ns + (0.06 ns/pF)CL -
13 26 ns
50 25 -
ns
25 12 -
ns
20 9
-
ns
60 30 -
ns
30 15 -
ns
25 12 -
ns
80 40 -
ns
40 20 -
ns
35 17 -
ns
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
Table 9. Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol Parameter
VDD
Typical formula for PD (W)
where:
PD
dynamic power 5 V
PD = 1000 fi + (fo CL) VDD2
fi = input frequency in MHz;
dissipation
10 V
PD = 4000 fi + (fo CL) VDD2
fo = output frequency in MHz;
15 V
PD = 10000 fi + (fo CL) VDD2
CL = output load capacitance in pF;
VDD = supply voltage in V;
(fo CL) = sum of the outputs.
HEF4511B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 11 November 2011
© NXP B.V. 2011. All rights reserved.
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