M38504M6-XXXFP 데이터 시트보기 (PDF) - Renesas Electronics

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M38504M6-XXXFP

8-BIT CISC SINGLE-CHIP MICROCOMPUTER

Renesas Electronics 

APPENDIX

3.7 Machine instructions

Symbol

LSR

MUL

NOP

ORA

(Note 1)

PHA

PHP

PLA

PLP

ROL

Addressing mode

Function

Details

IMP

IMM

A

BIT, A

ZP

BIT, ZP

OP n # OP n # OP n # OP n # OP n # OP n #

70

0→ →C

This instruction shifts either A or M one bit to

the right such that bit 7 of the result always is

set to 0, and the bit 0 is stored in C.

4A 2 1

46 5 2

M(S) • A ← A ✽ M(zz + X)

S←S–1

Multiplies Accumulator with the memory speci-

fied by the Zero Page X address mode and

stores the high-order byte of the result on the

Stack and the low-order byte in A.

PC ← PC + 1

This instruction adds one to the PC but does EA 2 1

no otheroperation.

When T = 0

A←AVM

When T = 1

M(X) ← M(X) V M

When T = 0, this instruction transfers the con-

tents of A and M to the ALU which performs a

bit-wise “OR”, and stores the result in A.

When T = 1, this instruction transfers the con-

tents of M(X) and the M to the ALU which

performs a bit-wise OR, and stores the result

in M(X). The contents of A remain unchanged,

but status flags are changed.

M(X) represents the contents of memory

where is indicated by X.

09 2 2

05 3 2

S←S–1

This instruction pushes the contents of A to

the memory location designated by S, and 48 3 1

decrements the contents of S by one.

M(S) ← PS

S←S–1

This instruction pushes the contents of PS to

the memory location designated by S and dec- 08 3 1

rements the contents of S by one.

S←S+1

A ← M(S)

This instruction increments S by one and

stores the contents of the memory designated 68 4 1

by S in A.

S←S+1

PS ← M(S)

This instruction increments S by one and

stores the contents of the memory location 28 4 1

designated by S in PS.

70

← ←C←

This instruction shifts either A or M one bit left

through C. C is stored in bit 0 and bit 7 is

stored in C.

2A 2 1

26 5 2

ROR

70

C→ →

This instruction shifts either A or M one bit

right through C. C is stored in bit 7 and bit 0 is

stored in C.

6A 2 1

66 5 2

RRF

70

→→

This instruction rotates 4 bits of the M content

to the right.

82 8 2

RTI

RTS

S←S+1

PS ← M(S)

S←S+1

PCL ← M(S)

S←S+1

PCH ← M(S)

S←S+1

PCL ← M(S)

S←S+1

PCH ← M(S)

(PC) ← (PC) + 1

This instruction increments S by one, and

stores the contents of the memory location 40 6 1

designated by S in PS. S is again incremented

by one and stores the contents of the memory

location designated by S in PCL. S is again

incremented by one and stores the contents of

memory location designated by S in PCH.

This instruction increments S by one and

stores the contents of the memory location 60 6 1

designated by S in PCL. S is again

incremented by one and the contents of the

memory location is stored in PCH. PC is

incremented by 1.

APPENDIX

3.7 Machine instructions

Addressing mode

Processor status register

ZP, X

ZP, Y

ABS ABS, X ABS, Y

IND ZP, IND IND, X IND, Y

REL

SP 7 6 5 4 3 2 1 0

OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # N V T B D I Z C

56 6 2

4E 6 3 5E 7 3

0 • • • • • ZC

62 15 2

••••••••

15 4 2

0D 4 3 1D 5 3 19 5 3

01 6 2 11 6 2

••••••••

N• • • • •Z•

36 6 2

76 6 2

2E 6 3 3E 7 3

6E 6 3 7E 7 3

••••••••

••••••••

N• • • • •Z•

(Value saved in stack)

N • • • • • ZC

N • • • • • ZC

••••••••

(Value saved in stack)

••••••••

3-74

3850 Group (Spec. H) User’s Manual

3850 Group (Spec. H) User’s Manual

3-75

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