M38504M6-XXXFP 데이터 시트보기 (PDF) - Renesas Electronics

부품명

상세내역

일치하는 목록

M38504M6-XXXFP

8-BIT CISC SINGLE-CHIP MICROCOMPUTER

Renesas Electronics 

APPENDIX

3.7 Machine instructions

3.7 Machine instructions

Addressing mode

Symbol

Function

Details

IMP

IMM

A

BBITI,TA, A, R ZP BBITI,TZ, PZP, R

OP n # OP n # OP n # OP n # OP n # OP n #

ADC

(Note 1)

(Note 5)

When T = 0

A←A+M+C

When T = 1

M(X) ← M(X) + M + C

When T = 0, this instruction adds the contents

M, C, and A; and stores the results in A and C.

When T = 1, this instruction adds the contents

of M(X), M and C; and stores the results in

M(X) and C. When T=1, the contents of A re-

main unchanged, but the contents of status

flags are changed.

M(X) represents the contents of memory

where is indicated by X.

69 2 2

65 3 2

AND

(Note 1)

WA h←enATV=M0

When T

M(X) ←

=1

M(X)

V

M

When T = 0, this instruction transfers the con-

tents of A and M to the ALU which performs a

bit-wise AND operation and stores the result

back in A.

When T = 1, this instruction transfers the con-

tents M(X) and M to the ALU which performs a

bit-wise AND operation and stores the results

back in M(X). When T = 1 the contents of A re-

main unchanged, but status flags are

changed.

M(X) represents the contents of memory

where is indicated by X.

29 2 2

25 3 2

ASL

70

C←

←0

This instruction shifts the content of A or M by

one bit to the left, with bit 0 always being set to

0 and bit 7 of A or M always being contained in

C.

0A 2 1

06 5 2

BBC

Ai or Mi = 0?

(Note 4)

This instruction tests the designated bit i of M

or A and takes a branch if the bit is 0. The

branch address is specified by a relative ad-

dress. If the bit is 1, next instruction is

executed.

1+3 4 2

20i

1+7 5 3

20i

BBS

Ai or Mi = 1?

(Note 4)

BCC

C = 0?

(Note 4)

BCS

C = 1?

(Note 4)

BEQ

Z = 1?

(Note 4)

V

BIT

AM

BMI

N = 1?

(Note 4)

BNE

Z = 0?

(Note 4)

This instruction tests the designated bit i of the

M or A and takes a branch if the bit is 1. The

branch address is specified by a relative ad-

dress. If the bit is 0, next instruction is

executed.

This instruction takes a branch to the ap-

pointed address if C is 0. The branch address

is specified by a relative address. If C is 1, the

next instruction is executed.

This instruction takes a branch to the ap-

pointed address if C is 1. The branch address

is specified by a relative address. If C is 0, the

next instruction is executed.

This instruction takes a branch to the ap-

pointed address when Z is 1. The branch

address is specified by a relative address.

If Z is 0, the next instruction is executed.

This instruction takes a bit-wise logical AND of

A and M contents; however, the contents of A

and M are not modified.

The contents of N, V, Z are changed, but the

contents of A, M remain unchanged.

This instruction takes a branch to the ap-

pointed address when N is 1. The branch

address is specified by a relative address.

If N is 0, the next instruction is executed.

This instruction takes a branch to the ap-

pointed address if Z is 0. The branch address

is specified by a relative address. If Z is 1, the

next instruction is executed.

0+3 4 2

20i

0+7 5 3

20i

24 3 2

3-68

3850 Group (Spec. H) User’s Manual

APPENDIX

3.7 Machine instructions

Addressing mode

Processor status register

ZP, X

ZP, Y

ABS ABS, X ABS, Y

IND ZP, IND IND, X IND, Y

REL

SP 7 6 5 4 3 2 1 0

OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # OP n # N V T B D I Z C

75 4 2

6D 4 3 7D 5 3 79 5 3

61 6 2 71 6 2

NV • • • • ZC

35 4 2

2D 4 3 3D 5 3 39 5 3

21 6 2 31 6 2

N• • • • •Z•

16 6 2

0E 6 3 1E 7 3

2C 4 3

N • • • • • ZC

••••••••

••••••••

90 2 2

B0 2 2

F0 2 2

••••••••

••••••••

••••••••

M7 M6 • • • • Z •

30 2 2

D0 2 2

••••••••

••••••••

3850 Group (Spec. H) User’s Manual

3-69

Share Link: