APPENDIX
3.5 List of registers
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 3D16)
b
Name
Functions
At reset R W
0 Timer 1 interrupt 0 : No interrupt request issued 0
✽
request bit
1 : Interrupt request issued
1 Timer 2 interrupt 0 : No interrupt request issued 0
✽
request bit
1 : Interrupt request issued
2 Serial I/O1 receive 0 : No interrupt request issued 0
✽
interrupt request bit 1 : Interrupt request issued
3 Serial I/O1 transmit 0 : No interrupt request issued 0
✽
interrupt request bit 1 : Interrupt request issued
4 CNTR0 interrupt 0 : No interrupt request issued 0
✽
request bit
1 : Interrupt request issued
5 CNTR1 interrupt 0 : No interrupt request issued 0
✽
request bit
1 : Interrupt request issued
6 A-D converter
0 : No interrupt request issued 0
✽
interrupt request bit 1 : Interrupt request issued
7 Nothing is arranged for this bit. This is a write
0
disabled bit. When this bit is read out, the
contents are “0”.
✽: “0” can be set by software, but “1” cannot be set.
Fig. 3.5.28 Structure of Interrupt request register 2
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Interrupt control register 1
(ICON1 : address 3E16)
b
Name
0 INT0 interrupt
enable bit
1 Fix this bit to “0”.
Functions
0 : Interrupt disabled
1 : Interrupt enabled
2 INT1 interrupt
enable bit
3 INT2 interrupt
enable bit
4 INT3/Serial I/O2
interrupt enable bit
5 Fix this bit to “0”.
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
6 Timer X interrupt
enable bit
7 Timer Y interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Fig. 3.5.29 Structure of Interrupt control register 1
At reset R W
0
0
0
0
0
0
0
0
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3850 Group (Spec. H) User’s Manual