CXD2500BQ 데이터 시트보기 (PDF) - Sony Semiconductor

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CXD2500BQ

CD Digital Signal Processor

Sony Semiconductor 

$AX Command

Command

Audio CTRL

CXD2500BQ

Data 1

D3

D2

D1

D0

Vari

Vari

Mute

ATT

UP

DWN

Data 2

D3

D2

PCT1

PCT2

Vari UP

Vari DWN

Pitch XTal 0% VCO 0% +0.1% +0.2% +0.3% +0.2% +0.1% +0% -0.1% -0.2%

XTal 0%

Command bit

Meaning

Mute=0 Muting is off unless condition to make muting occurs.

Mute=1 Muting is on. Peak register reset.

Command bit

Meaning

ATT=0 Attenuation is off.

ATT=1 –12dB

Condition for Muting

(1) Mute=1 in register A

(2) Pin Mute=1

(3) D.OUT Mute F=1 in register 8 with D.Out ON (MD2=1)

(4) Elapse of over 35 msec after GFS turns “Low”

(5) BiliGL MAIN=Sub=1 in register 9

(6) PCT1=1 and PCT2=2 in register A

In the case of (1) to (4), zero-cross muting not exceeding 1 msec is performed.

Command bit

PCT1

PCT2

Meaning

PCM Gain

0

0

Normal mode

×0 dB

0

1

Level meter mode

×0 dB

1

0

Peak meter mode

Mute

1

1

Normal mode

×0 dB

ECC correction capacity

C1: Double, C2: Quadruple

C1: Double, C2: Quadruple

C1: Double, C2: Double

C1: Double, C2: Double

Level Meter Mode (See Timing Chart 1-4.)

• This mode makes the digital level meter function available.

• Inputting 96-bit clock pulses to SQCK will enable 96 data to be output to SQSO. Of the output data, the first

80 bits comprise Sub-Q data, which transmit the description for the data format to the Sub Code interface.

The last 16 bits are ordered LSB-first, of which the first 15 bits constitute PCM data (absolute value). The

final 1 bit is “High” if the prior PCM data was generated at the left channel; “Low” if generated at the right

channel.

• The PCM data is reset once it is read, and the L/R flag is reversed. While this state is kept until the next

read operation is started, testing for the maximum value is conducted.

—17—

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