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MAX1202ACAP

5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface

Maxim Integrated 

MAX1202/MAX1203

5V, 8-Channel, Serial, 12-Bit ADCs

with 3V Digital Interface

Figure 11a shows the serial-interface timing necessary to

perform a conversion every 15 SCLK cycles in external

clock mode. If CS is low and SCLK is continuous, guar-

antee a start bit by first clocking in 16 zeros.

Most microcontrollers (μCs) require that data transfers

occur in multiples of eight clock cycles; 16 clocks per

conversion is typically the fastest that a μC can drive

the MAX1202/MAX1203. Figure 11b shows the serial-

interface timing necessary to perform a conversion every

16 SCLK cycles in external clock mode.

Applications Information

Power-On Reset

When power is first applied and if SHDN is not pulled low,

internal power-on reset circuitry activates the MAX1202/

MAX1203 in internal clock mode, ready to convert with

SSTRB = high. After the power supplies are stabilized, the

internal reset time is 100μs. No conversions should be per-

formed during this phase. SSTRB is high on power-up, and

if CS is low, the first logical 1 on DIN is interpreted as a start

bit. Until a conversion takes place, DOUT shifts out zeros.

Reference-Buffer Compensation

In addition to its shutdown function, SHDN also selects

internal or external compensation. The compensation

affects both power-up time and maximum conversion

speed. Compensated or not, the minimum clock rate is

100kHz due to droop on the sample-and-hold.

Leave SHDN unconnected to select external compensa-

tion. The Typical Operating Circuit uses a 4.7μF capacitor

at REF. A value of 4.7μF or greater ensures stability and

allows converter operation at the 2MHz full clock speed.

External compensation increases power-up time (see the

section Choosing Power-Down Mode, and Table 5).

Internal compensation requires no external capacitor

at REF, and is selected by pulling SHDN high. Internal

compensation allows for the shortest power-up times, but

the external clock must be limited to 400kHz during the

conversion.

Power-Down

Choosing Power-Down Mode

You can save power by placing the converter in a low-

current shutdown state between conversions. Select full

power-down or fast power-down mode via bits 1 and 0

of the DIN control byte with SHDN high or unconnected

(Tables 2 and 6). Pull SHDN low at any time to shut down

the converter completely. SHDN overrides bits 1 and 0 of

the control byte.

Full power-down mode turns off all chip functions that draw

quiescent current, reducing IDD and ISS typically to 2μA.

For the MAX1202, fast power-down mode turns off all

circuitry except the bandgap reference. With fast power-

down mode, the supply current is 30μA. Power-up time

can be shortened to 5μs in internal compensation mode.

Since the MAX1203 does not have an internal reference,

power-up times coming out of full or fast power-down are

identical.

IDD shutdown current can increase if any digital input

(DIN, SCLK, CS) is held high in either power-down mode.

The actual shutdown current depends on the state of the

digital inputs, the voltage applied to the digital inputs (VIH),

the supply voltage (VDD), and the operating temperature.

Figure 12c shows the maximum IDD increase for each

digital input held high in power-down mode for different

operating conditions. This current is cumulative, so if all

three digital inputs are held high, the additional shutdown

current is three times the value shown in Figure 12c.

In both software power-down modes, the serial interface

remains operational, but the ADC does not convert.

Table 5 shows how the choice of reference-buffer com-

pensation and power-down mode affects both power-up

delay and maximum sample rate. In external compensa-

tion mode, power-up time is 20ms with a 4.7μF compen-

sation capacitor (200ms with a 33μF capacitor) when the

capacitor is initially fully discharged. From fast power-

down, start-up time can be eliminated by using low-

leakage capacitors that do not discharge more than 1/2

LSB while shut down. In power-down, the capacitor has

to supply the current into the reference (typically 1.5μA)

and the transient currents at power-up.

Figures 12a and 12b show the various power-down

sequences in both external and internal clock modes.

Software Power-Down

Software power-down is activated using bits PD1 and

PD0 of the control byte. As shown in Table 6, PD1 and

PD0 also specify the clock mode. When software power-

down is asserted, the ADC continues to operate in the

last specified clock mode until the conversion is complete.

The ADC then powers down into a low quiescent-current

state. In internal clock mode, the interface remains active

and conversion results can be clocked out even though

the MAX1202/MAX1203 have already entered software

power-down.

The first logical 1 on DIN is interpreted as a start bit and

powers up the MAX1202/MAX1203. Following the start

bit, the control byte also determines clock and power-

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