MAX1202ACAP 데이터 시트보기 (PDF) - Maxim Integrated

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MAX1202ACAP

5V, 8-Channel, Serial, 12-Bit ADCs with 3V Digital Interface

Maxim Integrated 

MAX1202/MAX1203

5V, 8-Channel, Serial, 12-Bit ADCs

with 3V Digital Interface

CS

SCLK

DIN

DOUT

tCSS

tCSH

tDS

tDH

tDV

Figure 7. Detailed Serial-Interface Timing

•••

tCH

tCL

•••

•••

•••

tCSH

tDO

tTR

CS

SSTRB

•••

tSDV

•••

•••

tSTR

•••

tSSTRB

tSSTRB

SCLK

•••

•••

PD0 CLOCKED IN

Figure 8. External Clock Mode SSTRB Detailed Timing

the next CS falling edge, SSTRB outputs a logic low.

Figure 8 shows SSTRB timing in external clock mode.

The conversion must complete in some minimum time or

droop on the sample-and-hold capacitors might degrade

conversion results. Use internal clock mode if the clock

period exceeds 10μs or if serial-clock interruptions could

cause the conversion interval to exceed 120μs.

Internal Clock

In internal clock mode, the MAX1202/MAX1203 generate

their own conversion clock. This frees the μP from run-

ning the SAR conversion clock, and allows the conversion

results to be read back at the processor’s convenience,

at any clock rate from zero to 2MHz. SSTRB goes low

at the start of the conversion, then goes high when the

conversion is complete. SSTRB is low for a maximum

of 10μs, during which time SCLK should remain low for

best noise performance. An internal register stores data

while the conversion is in progress. SCLK clocks the

data out at this register at any time after the conversion

is complete. After SSTRB goes high, the next falling clock

edge produces the MSB of the conversion at DOUT, fol-

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